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Re: [libc-alpha] Re: PATCH: Fix ll/sc for mips
- From: Geoff Keating <geoffk at geoffk dot org>
- To: schwab at suse dot de
- Cc: machida at sm dot sony dot co dot jp, kaz at ashi dot footprints dot net, hjl at lucon dot org, macro at ds2 dot pg dot gda dot pl, libc-alpha at sources dot redhat dot com, linux-mips at oss dot sgi dot com
- Date: Fri, 1 Feb 2002 03:23:43 -0800
- Subject: Re: [libc-alpha] Re: PATCH: Fix ll/sc for mips
- References: <20020201.123523.50041631.machida@sm.sony.co.jp><Pine.LNX.4.33.0201311952440.2305-100000@ashi.FootPrints.net><20020201.135903.123568420.machida@sm.sony.co.jp> <jebsf9bhot.fsf@sykes.suse.de>
- Reply-to: Geoff Keating <geoffk at redhat dot com>
> From: Andreas Schwab <schwab@suse.de>
> Date: Fri, 01 Feb 2002 11:49:22 +0100
> There is no way to find out anything about intermediate values of *p when
> compare_and_swap returns zero. The value of *p can change anytime, even
> if it only was different from oldval just at the time compare_and_swap did
> the comparison. So there is zero chance that a spurious failure of
> compare_and_swap breaks anything.
Something to watch out for, though, is livelock. Consider the
situation in which two processors are competing for a cache line, and
both only win at the 'wrong' time: when computing a new value to be
passed to compare_and_swap rather than when actually trying to perform
the compare_and_swap. This is why on powerpc the loop is coded in the
asm statement.
--
- Geoffrey Keating <geoffk@geoffk.org> <geoffk@redhat.com>