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On Wed, 2003-10-29 at 10:20, Radu Cernea wrote: > > Fair enough - please send a proper patch for this, along with the > > ChangeLog entry. It would also be nice to see the corresponding > > patch for the interrupt driven serial driber. > > > > Note: use something like this: > > #if defined(CYGHWR_HAL_POWERPC_860) || defined(CYGHWR_HAL_POWERPC_860T) > > ... your proposed setup > > #else > > .. current setup > > #endif > > The attached file is the patch for fixing the SMC2 port pins initialization > for MPC860 and MPC821 uP. Unfortunately, I do not have CVS access, so the > patch is based on ecos-trunk-031026.tar.bz2 downloaded from ecosccentric, not > on the latest CVS version, as it should. Hopefully there are no differences > here... > > I also changed the file > ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c, but I > do not have a MPC850 board to test these changes. In this file, the SMC2 port > initialization was proper only for the MPC860-like processors. I made a few [cosmetic] changes to your patch. Can you test this and let me know if it works for you? -- Gary Thomas <gary@chez-thomas.org>
Index: hal/powerpc/quicc/current/src/quicc_smc1.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c,v
retrieving revision 1.29
diff -u -5 -p -r1.29 quicc_smc1.c
--- hal/powerpc/quicc/current/src/quicc_smc1.c 8 Sep 2003 14:55:36 -0000 1.29
+++ hal/powerpc/quicc/current/src/quicc_smc1.c 5 Nov 2003 16:03:42 -0000
@@ -149,28 +149,37 @@ cyg_hal_smcx_init_channel(struct port_in
#if CYGNUM_HAL_QUICC_SMC1 > 0
case QUICC_CPM_SMC1:
/*
* Set up the PortB pins for UART operation.
* Set PAR and DIR to allow SMCTXD1 and SMRXD1
- * (Table 16-39)
+ * (Table 34-1 MPC850UM) or (Table 33-6 MPC860UM)
*/
eppc->pip_pbpar |= 0xc0;
eppc->pip_pbdir &= ~0xc0;
-
break;
#endif
#if CYGNUM_HAL_QUICC_SMC2 > 0
case QUICC_CPM_SMC2:
+#if defined(CYGHWR_HAL_POWERPC_850) || defined(CYGHWR_HAL_POWERPC_823)
/*
* Set up the PortA pins for UART operation.
* Set PAR and DIR to allow SMCTXD2 and SMRXD2
- * (Table 16-39)
+ * (Table 34-1 MPC850UM)
*/
eppc->pio_papar |= 0xc0;
eppc->pio_padir &= ~0xc0;
eppc->pio_paodr &= ~0xc0;
-
+#else
+ /*
+ * Set up the PortB pins for UART operation.
+ * Set PAR and DIR to allow SMCTXD2 and SMRXD2
+ * (Table 33-6 MPC860UM)
+ */
+ eppc->pip_pbpar |= 0xc00;
+ eppc->pip_pbdir &= ~0xc00;
+ eppc->pip_pbodr &= ~0xc00;
+#endif
break;
#endif
}
// Set up baud rate generator. These are allocated from a
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.17
diff -u -5 -p -r1.17 quicc_smc_serial.c
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 13 Oct 2003 15:36:15 -0000 1.17
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 5 Nov 2003 16:26:20 -0000
@@ -363,19 +363,21 @@ quicc_smc_serial_config_port(serial_chan
}
return true;
}
// Function to set up internal tables for device.
+#define USE_PORTA 0
+#define USE_PORTB 1
static void
quicc_smc_serial_init_info(quicc_sxx_serial_info *smc_chan,
volatile struct smc_uart_pram *uart_pram,
volatile struct smc_regs *ctl,
int TxBD, int TxNUM, int TxSIZE,
cyg_uint8 *TxBUF,
int RxBD, int RxNUM, int RxSIZE,
cyg_uint8 *RxBUF,
- int portBmask,
+ int portmask, int portsel,
int port)
{
EPPC *eppc = eppc_base();
struct cp_bufdesc *txbd, *rxbd;
int i;
@@ -388,16 +390,21 @@ quicc_smc_serial_init_info(quicc_sxx_ser
// Disable channel during setup
ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
/*
- * Set up the PortB pins for UART operation.
+ * Set up the Port (port A or B depending on CPU) pins for UART operation
* Set PAR and DIR to allow SMCTXDx and SMRXDx
- * (Table 16-39)
+ * (Table 34-1 MPC850UM) or (Table 33-6 MPC860UM)
*/
- eppc->pip_pbpar |= portBmask;
- eppc->pip_pbdir &= ~portBmask;
+ if (portsel == USE_PORTA) {
+ eppc->pio_papar |= portmask;
+ eppc->pio_padir &= ~portmask;
+ } else {
+ eppc->pip_pbpar |= portmask;
+ eppc->pip_pbdir &= ~portmask;
+ }
/*
* SDMA & LCD bus request level 5
* (Section 16.10.2.1)
*/
eppc->dma_sdcr = 1;
@@ -643,11 +650,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
&quicc_smc1_txbuf[0],
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
&quicc_smc1_rxbuf[0],
- 0xC0, // PortB mask
+ 0xC0, USE_PORTB, // PortB mask
QUICC_CPM_SMC1
);
}
#endif
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2
@@ -663,22 +670,26 @@ quicc_sxx_serial_init(struct cyg_devtab_
&quicc_smc2_txbuf[0],
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
&quicc_smc2_rxbuf[0],
- 0xC00, // PortB mask
+#if defined(CYGHWR_HAL_POWERPC_850) || defined(CYGHWR_HAL_POWERPC_823)
+ 0xC0, USE_PORTA, // PortA mask
+#else
+ 0xC00, USE_PORTB, // PortB mask
+#endif
QUICC_CPM_SMC2
);
}
#endif
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC1
if (chan == &quicc_sxx_serial_channel_scc1) {
TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM);
RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM);
quicc_scc_serial_init_info(&quicc_sxx_serial_info_scc1,
&eppc->pram[0].scc.pscc.u, // PRAM
- &eppc->scc_regs[0], // Control registersn
+ &eppc->scc_regs[0], // Control registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE,
&quicc_scc1_txbuf[0],
RxBD,
@@ -696,11 +707,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
if (chan == &quicc_sxx_serial_channel_scc2) {
TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM);
RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM);
quicc_scc_serial_init_info(&quicc_sxx_serial_info_scc2,
&eppc->pram[1].scc.pscc.u, // PRAM
- &eppc->scc_regs[1], // Control registersn
+ &eppc->scc_regs[1], // Control registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE,
&quicc_scc2_txbuf[0],
RxBD,
@@ -718,11 +729,11 @@ quicc_sxx_serial_init(struct cyg_devtab_
if (chan == &quicc_sxx_serial_channel_scc3) {
TxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM);
RxBD = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM);
quicc_scc_serial_init_info(&quicc_sxx_serial_info_scc3,
&eppc->pram[2].scc.pscc.u, // PRAM
- &eppc->scc_regs[2], // Control registersn
+ &eppc->scc_regs[2], // Control registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE,
&quicc_scc3_txbuf[0],
RxBD,
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