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Adding Analogue & Micro Rattler - Motorola MPC8250 -- Gary Thomas <gary@mlbassoc.com> MLB Associates
Index: ecos.db
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ecos.db,v
retrieving revision 1.101
diff -u -5 -p -r1.101 ecos.db
--- ecos.db 18 Aug 2003 08:22:02 -0000 1.101
+++ ecos.db 19 Aug 2003 14:52:04 -0000
@@ -1007,10 +1007,18 @@ package CYGPKG_IO_SERIAL_SH_SCIF {
directory devs/serial/sh/scif
script ser_sh_scif.cdl
description "SH SCIF serial device drivers"
}
+package CYGPKG_DEVS_ETH_PHY {
+ alias { "Generic PHY support" eth_phy_support }
+ hardware
+ directory devs/eth/phy
+ script phy_eth_drivers.cdl
+ description "PHY (ethernet physical transciever) API."
+}
+
package CYGPKG_DEVS_ETH_ARM_CERF {
alias { "Crystal LAN ethernet driver for Cerf boards" cerf_eth_driver }
hardware
directory devs/eth/arm/cerf
script cerf_eth_drivers.cdl
@@ -1420,10 +1428,18 @@ package CYGPKG_DEVS_ETH_POWERPC_FEC {
directory devs/eth/powerpc/fec
script fec_eth_drivers.cdl
description "Ethernet driver for PowerPC FEC (MPC8xxT) based boards."
}
+package CYGPKG_DEVS_ETH_POWERPC_FCC {
+ alias { "FCC ethernet driver" fcc_eth_driver }
+ hardware
+ directory devs/eth/powerpc/fcc
+ script fcc_eth_drivers.cdl
+ description "Fast ethernet driver for PowerPC MPCxxx based boards."
+}
+
package CYGPKG_DEVS_ETH_POWERPC_VIPER {
alias { "A&M Viper ethernet driver" viper_eth_driver }
hardware
directory devs/eth/powerpc/viper
script viper_eth_drivers.cdl
@@ -2794,10 +2810,21 @@ package CYGPKG_HAL_POWERPC_MPC8260 {
The PowerPC MPC8260 PowerQUICCII variant HAL package provides
support for this processor variant. It is also necessary to
select a specific target platform HAL package."
}
+package CYGPKG_HAL_POWERPC_MPC8XXX {
+ alias { "PowerPC MPC8XXX variant HAL" hal_mpc8xxx }
+ directory hal/powerpc/mpc8xxx/
+ script hal_powerpc_mpc8xxx.cdl
+ hardware
+ description "
+ The PowerPC MPC8XXX PowerQUICCII variant HAL package provides
+ support for this processor variant. It is also necessary to
+ select a specific target platform HAL package."
+}
+
package CYGPKG_HAL_POWERPC_MPC8xx {
alias { "PowerPC 8xx variant HAL" hal_mpc8xx mpc8xx_hal mpc8xx_arch_hal }
directory hal/powerpc/mpc8xx/
script hal_powerpc_mpc8xx.cdl
hardware
@@ -4899,6 +4926,52 @@ target adderII {
}
enable { CYGHWR_HAL_POWERPC_ADDER_II }
description "
The adderII target provides the packages needed to run
eCos on a A&M Adder PPC852T board."
+}
+
+# --------------------------------------------------------------------------
+
+package CYGPKG_HAL_POWERPC_RATTLER {
+ alias { "A&M Rattler MPC8250 board" hal_powerpc_rattler powerpc_rattler_hal }
+ directory hal/powerpc/rattler
+ script hal_powerpc_rattler.cdl
+ hardware
+ description "
+ The RATTLER HAL package provides the support needed to run
+ eCos on a A&M RATTLER board equipped with a PowerPC processor."
+}
+
+package CYGPKG_DEVS_ETH_POWERPC_RATTLER {
+ alias { "A&M Rattler ethernet driver" rattler_eth_driver }
+ hardware
+ directory devs/eth/powerpc/rattler
+ script rattler_eth_drivers.cdl
+ description "Ethernet driver specifics for A&M Rattler (MPC8250) based boards."
+}
+
+package CYGPKG_DEVS_FLASH_POWERPC_RATTLER {
+ alias { "FLASH memory support for A&M Rattler (MPC8250)" flash_rattler }
+ directory devs/flash/powerpc/rattler
+ script flash_rattler.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the A&M Rattler (MPC8250) platforms."
+}
+
+target rattler {
+ alias { "A&M Rattler (8250) board" }
+ packages { CYGPKG_HAL_POWERPC
+ CYGPKG_HAL_POWERPC_MPC8XXX
+ CYGPKG_HAL_POWERPC_RATTLER
+ CYGPKG_DEVS_FLASH_POWERPC_RATTLER
+ CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+ CYGPKG_DEVS_ETH_POWERPC_FCC
+ CYGPKG_DEVS_ETH_POWERPC_RATTLER
+ CYGPKG_DEVS_ETH_PHY
+ }
+ description "
+ The rattler target provides the packages needed to run
+ eCos on an Analogue & Micro Rattler (MPC8250) board."
}
Index: NEWS
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/NEWS,v
retrieving revision 1.74
diff -u -5 -p -r1.74 NEWS
--- NEWS 5 Jun 2003 13:21:24 -0000 1.74
+++ NEWS 19 Aug 2003 16:30:40 -0000
@@ -1,5 +1,9 @@
+* New port to Analogue & Micro Rattler (Motorola MPC8250)
+* Improved support for ethernet PHY devices.
+* Improved variant support for Motorola Power-QUICC2 systems.
+* Vastly improved networking speeds in RedBoot stack.
* New port for Motorola PrPMC1100 (Intel XScale IXC1100)
* SNTP client supports IPv6 multicast packets from time servers.
* DNS client support looking up IPv6 addresses and reverse lookups
* FTP client is IPv6 aware.
* httpd daemon is IPv6 aware.
Index: devs/eth/powerpc/fcc/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/fcc/current/ChangeLog
diff -N devs/eth/powerpc/fcc/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/ChangeLog 19 Aug 2003 16:34:38 -0000
@@ -0,0 +1,46 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * src/if_fcc.c:
+ * src/fcc.h:
+ * cdl/fcc_eth_drivers.cdl: New file(s) - generic ethernet driver
+ for Motorola QUICC-2 FCC controller. Roughly based on previously
+ contributed devs/eth/powerpc/quicc2 package.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+
+
Index: devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl
diff -N devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/cdl/fcc_eth_drivers.cdl 19 Aug 2003 16:13:05 -0000
@@ -0,0 +1,132 @@
+# ====================================================================
+#
+# fcc_eth_drivers.cdl
+#
+# Ethernet drivers - variant dependent support for PowerPC MPC8xxx
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002, 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data:
+# Contributors:
+# Date: 2003-08-19
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_FCC {
+ display "MPC8xxx FCC ethernet driver"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_HAL_POWERPC
+ active_if CYGPKG_HAL_POWERPC_MPC8XXX
+
+ include_dir .
+ include_files ; # none _exported_ whatsoever
+
+ description "Fast ethernet driver for PowerPC MPC8xxx boards."
+ compile -library=libextras.a if_fcc.c
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE {
+ display "Buffer size"
+ flavor data
+ default_value 1540
+ description "
+ This option specifies the size of the internal buffers used
+ for the PowerPC FCC/ethernet device."
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM {
+ display "Number of output buffers"
+ flavor data
+ legal_values 2 to 64
+ default_value 8
+ description "
+ This option specifies the number of output buffer packets
+ to be used for the PowerPC FCC/ethernet device."
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM {
+ display "Number of input buffers"
+ flavor data
+ legal_values 2 to 64
+ default_value 8
+ description "
+ This option specifies the number of input buffer packets
+ to be used for the PowerPC FCC/ethernet device."
+ }
+
+ cdl_component CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY {
+ display "Reset and reconfigure PHY"
+ flavor bool
+ default_value { CYG_HAL_STARTUP != "RAM" }
+ active_if CYGPKG_DEVS_ETH_PHY
+ description "
+ This option allows control over the physical transceiver"
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_FCC_LINK_MODE {
+ display "Initial link mode"
+ flavor data
+ legal_values { "10Mb" "100Mb" "Auto" }
+ default_value { "Auto" }
+ description "
+ This option specifies initial mode for the physical
+ link. The PHY will be reset and then set to this mode."
+ }
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_POWERPC_FCC_OPTIONS {
+ display "MPC8xxx FCC ethernet driver build options"
+ flavor none
+ no_define
+
+ cdl_option CYGPKG_DEVS_ETH_POWERPC_FCC_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "-D_KERNEL -D__ECOS" }
+ description "
+ This option modifies the set of compiler flags for
+ building the MPC8xxx FCC ethernet driver package.
+ These flags are used in addition to the set of global
+ flags."
+ }
+ }
+}
Index: devs/eth/powerpc/fcc/current/src/fcc.h
===================================================================
RCS file: devs/eth/powerpc/fcc/current/src/fcc.h
diff -N devs/eth/powerpc/fcc/current/src/fcc.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/src/fcc.h 19 Aug 2003 16:13:37 -0000
@@ -0,0 +1,181 @@
+//==========================================================================
+//
+// fcc.h
+//
+// PowerPC MPC8xxx fast ethernet (FCC)
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: pfine, mtek
+// Date: 2003-08-19
+// Purpose:
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/devs_eth_powerpc_fcc.h>
+// The port connected to the ethernet
+#define FCC1 0
+#define FCC2 1
+
+/* ------------------------ */
+/* FCC REGISTER CONSTANTS */
+/* ------------------------ */
+
+// GFMR masks (RESET: 0x00000000)
+#define FCC_GFMR_EN_Rx 0x00000020 // Receive enable
+#define FCC_GFMR_EN_Tx 0x00000010 // Transmit enable
+#define FCC_GFMR_INIT 0x0000000C // mode=ethernet
+
+//PSMR masks (RESET: 0x00000000)
+#define FCC_PSMR_INIT 0x00000080 // 32-bit CRC
+
+//TODR masks (RESET: 0x0000)
+#define FCC_TOD_INIT 0x0000
+#define FCC_TOD_SET 0x8000
+
+//DSR masks (RESET: 0x7E7E)
+#define FCC_DSR_INIT 0xD555
+
+//FCCE & FCCM (RESET: 0x0000)
+#define FCC_EV_GRA 0x0080 // Graceful stop
+#define FCC_EV_RXC 0x0040 // A control frame has been received
+#define FCC_EV_TXC 0x0020 // Out of sequence frame sent
+#define FCC_EV_TXE 0x0010 // Error in transmission channel
+#define FCC_EV_RXF 0x0008 // A complete frame received
+#define FCC_EV_BSY 0x0004 // A received frame discarded due to lack
+ // of buffers
+#define FCC_EV_TXB 0x0002 // A buffer sent to ethernet
+#define FCC_EV_RXB 0x0001 // A buffer that is a non-complete frame
+ // is received
+
+/* ------------------------------ */
+/* FCC PARAMETER RAM CONSTANTS */
+/* ------------------------------ */
+
+#define FCC_FCR_INIT 0x00000000 // Clear the reserved bits
+#define FCC_FCR_MOT_BO 0x10000000 // Motorola byte ordering
+#define FCC_PRAM_C_MASK 0xDEBB20E3 // Constant MASK for CRC
+#define FCC_PRAM_C_PRES 0xFFFFFFFF // CRC Preset
+#define FCC_PRAM_RETLIM 15 // Retry limit
+#define FCC_PRAM_PER_LO 5 // Persistance
+#define FCC_PRAM_PER_HI 0
+#define FCC_PRAM_MRBLR 1536
+#define FCC_MAX_FLR 1518 // Max frame length
+#define FCC_MIN_FLR 64 // Min frame length
+#define FCC_PRAM_PAD_CH 0x8888
+#define FCC_PRAM_MAXD 1520
+#define FCC1_PRAM_OFFSET 0x8400 // Offset of t_Fcc_Pram in 82xx
+#define FCC2_PRAM_OFFSET 0x8500 // Offset of t_Fcc_Pram in 82xx
+
+/* ------------------------------ */
+/* BUFFER DESCRIPTOR CONSTANTS */
+/* ------------------------------ */
+#define FCC_BD_Rx_Empty 0x8000 // Buffer is empty, FCC can fill
+#define FCC_BD_Rx_Wrap 0x2000 // Wrap: Last buffer in ring
+#define FCC_BD_Rx_Int 0x1000 // Interrupt
+#define FCC_BD_Rx_Last 0x0800 // Last buffer in frame
+#define FCC_BD_Rx_Miss 0x0100 // Miss: promiscious mode
+#define FCC_BD_Rx_BC 0x0080 // Broadcast address
+#define FCC_BD_Rx_MC 0x0040 // Multicast address
+#define FCC_BD_Rx_LG 0x0020 // Frame length violation
+#define FCC_BD_Rx_NO 0x0010 // Non-octet aligned frame
+#define FCC_BD_Rx_SH 0x0008 // Short frame
+#define FCC_BD_Rx_CR 0x0004 // CRC error
+#define FCC_BD_Rx_OV 0x0002 // Overrun
+#define FCC_BD_Rx_TR 0x0001 // Frame truncated. late collision
+
+#define FCC_BD_Tx_Ready 0x8000 // Frame ready
+#define FCC_BD_Tx_Pad 0x4000 // Pad short frames
+#define FCC_BD_Tx_Wrap 0x2000 // Wrap: Last buffer in ring
+#define FCC_BD_Tx_Int 0x1000 // Interrupt
+#define FCC_BD_Tx_Last 0x0800 // Last buffer in frame
+#define FCC_BD_Tx_TC 0x0400 // Send CRC after data
+#define FCC_BD_Tx_DEF 0x0200 // Defer indication
+#define FCC_BD_Tx_HB 0x0100 // Heartbeat
+#define FCC_BD_Tx_LC 0x0080 // Late collision
+#define FCC_BD_Tx_RL 0x0040 // Retransmission limit
+#define FCC_BD_Tx_RC 0x003C // Retry count
+#define FCC_BD_Tx_UN 0x0002 // Underrun
+#define FCC_BD_Tx_CSL 0x0001 // Carrier sense lost
+#define FCC_BD_Tx_ERRORS (FCC_BD_Tx_LC|FCC_BD_Tx_RL|FCC_BD_Tx_RC|FCC_BD_Tx_UN|FCC_BD_Tx_CSL)
+
+
+// Buffer descriptor
+struct fcc_bd {
+ volatile unsigned short ctrl;
+ volatile unsigned short length;
+ volatile unsigned char *buffer;
+};
+
+//
+// Info kept about each interface
+//
+struct fcc_eth_info {
+ // These fields should be defined by the implementation
+ int int_vector;
+ char *esa_key; // RedBoot 'key' for device ESA
+ unsigned char enaddr[6];
+ int rxnum; // Number of Rx buffers
+ unsigned char *rxbuf; // Rx buffer space
+ int txnum; // Number of Tx buffers
+ unsigned char *txbuf; // Tx buffer space
+#ifdef CYGPKG_DEVS_ETH_PHY
+ eth_phy_access_t *phy; // Routines to access PHY
+#endif
+ // The rest of the structure is set up at runtime
+ volatile struct fcc_regs *fcc_reg; // See "mpc8260.h"
+ struct fcc_bd *txbd, *rxbd; // Next Tx,Rx descriptor to use
+ struct fcc_bd *tbase, *rbase; // First Tx,Rx descriptor
+ struct fcc_bd *tnext, *rnext; // Next descriptor to check for interrupt
+ int txsize, rxsize; // Length of individual buffers
+ unsigned long txkey[CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM];
+#ifdef CYGPKG_NET
+ cyg_interrupt fcc_eth_interrupt;
+ cyg_handle_t fcc_eth_interrupt_handle;
+#endif
+};
+
+// CPM_CPCR masks
+#define CPCR_GRSTOP_TX 0x00000005
+#define CPCR_MCN_FCC 0x00000300
+#define CPCR_READY_TO_RX_CMD 0 /* Ready to receive a command */
Index: devs/eth/powerpc/fcc/current/src/if_fcc.c
===================================================================
RCS file: devs/eth/powerpc/fcc/current/src/if_fcc.c
diff -N devs/eth/powerpc/fcc/current/src/if_fcc.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/fcc/current/src/if_fcc.c 19 Aug 2003 16:14:34 -0000
@@ -0,0 +1,675 @@
+//==========================================================================
+//
+// dev/if_fcc.c
+//
+// Fast ethernet device driver for PowerPC MPC8xxx (QUICC-II) boards
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: mtek, pfine
+// Date: 2003-08-19
+// Purpose:
+// Description: hardware driver for MPC8xxx FCC
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/devs_eth_powerpc_fcc.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/mpc8xxx.h>
+
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#ifdef CYGPKG_NET
+#include <pkgconf/net.h>
+#endif
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+#include <cyg/io/eth_phy.h>
+#endif
+
+#include "fcc.h"
+
+#ifdef CYGPKG_REDBOOT
+#include <pkgconf/redboot.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <redboot.h>
+#include <flash_config.h>
+#endif
+#endif
+
+#ifdef CYGDAT_DEVS_FCC_ETH_INL
+#include CYGDAT_DEVS_FCC_ETH_CDL // platform configury
+#include CYGDAT_DEVS_FCC_ETH_INL // platform details
+#else
+#error "No board instance defined!"
+#endif
+
+#define ALIGN_TO_CACHE_LINES(x) ( (long)((x) + 31) & 0xffffffe0 )
+
+// Buffer descriptors are in dual ported RAM, which is marked non-cached
+#define FCC_BDs_NONCACHED
+
+#define os_printf diag_printf
+
+// CONFIG_ESA and CONFIG_BOOL are defined in redboot/include/flash_config.h
+#ifndef CONFIG_ESA
+#define CONFIG_ESA 6 // ethernet address length ...
+#endif
+
+#ifndef CONFIG_BOOL
+#define CONFIG_BOOL 1
+#endif
+
+static void fcc_eth_int(struct eth_drv_sc *data);
+
+// This ISR is called when the ethernet interrupt occurs
+#ifdef CYGPKG_NET
+static int
+fcc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
+{
+ struct eth_drv_sc *sc = (struct eth_drv_sc *)data;
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+
+ cyg_drv_interrupt_mask(qi->int_vector);
+ return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
+}
+#endif
+
+// Deliver function (ex-DSR) handles the ethernet [logical] processing
+static void
+fcc_eth_deliver(struct eth_drv_sc * sc)
+{
+#ifdef CYGPKG_NET
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+#endif
+
+ fcc_eth_int(sc);
+#ifdef CYGPKG_NET
+ // Clearing the event register acknowledges FCC interrupt ...
+ cyg_drv_interrupt_unmask(qi->int_vector);
+#endif
+
+}
+
+
+// Initialize the interface - performed at system startup
+// This function must set up the interface, including arranging to
+// handle interrupts, etc, so that it may be "started" cheaply later.
+static bool
+fcc_eth_init(struct cyg_netdevtab_entry *dtp)
+{
+ struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *)0;
+ volatile t_EnetFcc_Pram *E_fcc;
+ int i, fcc_chan;
+ bool esa_ok;
+ unsigned char *c_ptr;
+ unsigned char _enaddr[6];
+ unsigned long rxbase, txbase;
+ struct fcc_bd *rxbd, *txbd;
+ // The FCC seems rather picky about these...
+ static long rxbd_base = 0x3000;
+ static long txbd_base = 0xB000;
+
+ // Set up pointers to FCC controller
+ switch (qi->int_vector) {
+ case CYGNUM_HAL_INTERRUPT_FCC1:
+ qi->fcc_reg = &(IMM->fcc_regs[FCC1]);
+ fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC1_PRAM_OFFSET);
+ fcc_chan = FCC1_PAGE_SUBBLOCK;
+ break;
+ case CYGNUM_HAL_INTERRUPT_FCC2:
+ qi->fcc_reg = &(IMM->fcc_regs[FCC2]);
+ fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC2_PRAM_OFFSET);
+ fcc_chan = FCC2_PAGE_SUBBLOCK;
+ break;
+ default:
+ os_printf("Can't initialize '%s' - unknown FCC!\n", dtp->name);
+ return false;
+ }
+
+ // just in case : disable Transmit and Receive
+ qi->fcc_reg->fcc_gfmr &= ~(FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
+
+ // Try to read the ethernet address of the transciever ...
+#ifdef CYGPKG_REDBOOT
+ esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
+#else
+ esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ qi->esa_key, _enaddr, CONFIG_ESA);
+#endif
+ if (esa_ok) {
+ memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
+ } else {
+ // No 'flash config' data available - use default
+ os_printf("FCC_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
+ }
+
+ // Initialize Receive Buffer Descriptors
+ rxbase = rxbd_base;
+ fcc->riptr = rxbase; // temp work buffer
+ fcc->mrblr = FCC_PRAM_MRBLR; // Max Rx buffer
+ fcc->rstate &= FCC_FCR_INIT;
+ fcc->rstate |= FCC_FCR_MOT_BO;
+ rxbase += 64;
+ rxbd_base += sizeof(struct fcc_bd)*qi->rxnum + 64;
+ rxbd = (struct fcc_bd *)(CYGARC_IMM_BASE + rxbase);
+ fcc->rbase = (CYG_WORD)rxbd;
+ c_ptr = qi->rxbuf;
+ qi->rbase = rxbd;
+ qi->rxbd = rxbd;
+ qi->rnext = rxbd;
+
+ for (i = 0; i < qi->rxnum; i++, rxbd++) {
+ rxbd->ctrl = (FCC_BD_Rx_Empty | FCC_BD_Rx_Int);
+ rxbd->length = 0; // reset
+ c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
+ rxbd->buffer = (volatile unsigned char *)c_ptr;
+ c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
+ }
+ rxbd--;
+ rxbd->ctrl |= FCC_BD_Rx_Wrap;
+
+ // Initialize Transmit Buffer Descriptors
+ txbase = txbd_base;
+ fcc->tiptr = txbase; // in dual port RAM (see 28-11)
+ fcc->tstate &= FCC_FCR_INIT;
+ fcc->tstate |= FCC_FCR_MOT_BO;
+ txbase += 64;
+ txbd_base += sizeof(struct fcc_bd)*qi->txnum + 64;
+ txbd = (struct fcc_bd *)(CYGARC_IMM_BASE + txbase);
+ fcc->tbase = (CYG_WORD)txbd;
+ c_ptr = qi->txbuf;
+ qi->tbase = txbd;
+ qi->txbd = txbd;
+ qi->tnext = txbd;
+
+ for (i = 0; i < qi->txnum; i++, txbd++) {
+ txbd->ctrl = (FCC_BD_Tx_Pad | FCC_BD_Tx_Int);
+ txbd->length = 0; // reset : Write before send
+ c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
+ txbd->buffer = (volatile unsigned char *)c_ptr;
+ c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
+ }
+ txbd--;
+ txbd->ctrl |= FCC_BD_Tx_Wrap;
+
+ // Ethernet Specific FCC Parameter RAM Initialization
+ E_fcc = &(fcc->SpecificProtocol.e);
+ E_fcc->c_mask = FCC_PRAM_C_MASK; // (see 30-9)
+ E_fcc->c_pres = FCC_PRAM_C_PRES;
+ E_fcc->crcec = 0;
+ E_fcc->alec = 0;
+ E_fcc->disfc = 0;
+ E_fcc->ret_lim = FCC_PRAM_RETLIM;
+ E_fcc->p_per = FCC_PRAM_PER_LO;
+ E_fcc->gaddr_h = 0;
+ E_fcc->gaddr_l = 0;
+ E_fcc->tfcstat = 0;
+ E_fcc->mflr = FCC_MAX_FLR;
+
+ E_fcc->paddr1_h = ((short)qi->enaddr[5] << 8) | qi->enaddr[4];
+ E_fcc->paddr1_m = ((short)qi->enaddr[3] << 8) | qi->enaddr[2];
+ E_fcc->paddr1_l = ((short)qi->enaddr[1] << 8) | qi->enaddr[0];
+
+ E_fcc->iaddr_h = 0;
+ E_fcc->iaddr_l = 0;
+ E_fcc->minflr = FCC_MIN_FLR;
+ E_fcc->taddr_h = 0;
+ E_fcc->taddr_m = 0;
+ E_fcc->taddr_l = 0;
+ E_fcc->pad_ptr = fcc->tiptr; // No special padding char ...
+ E_fcc->cf_type = 0;
+ E_fcc->maxd1 = FCC_PRAM_MAXD;
+ E_fcc->maxd2 = FCC_PRAM_MAXD;
+
+ // FCC register initialization
+ qi->fcc_reg->fcc_gfmr = FCC_GFMR_INIT;
+ qi->fcc_reg->fcc_psmr = FCC_PSMR_INIT;
+ qi->fcc_reg->fcc_dsr = FCC_DSR_INIT;
+
+#ifdef CYGPKG_NET
+ // clear the events of FCCX
+ qi->fcc_reg->fcc_fcce = 0xFFFF;
+ qi->fcc_reg->fcc_fccm = FCC_EV_TXE | FCC_EV_TXB | FCC_EV_RXF;
+
+ // Set up to handle interrupts
+ cyg_drv_interrupt_create(qi->int_vector,
+ 0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
+ (cyg_addrword_t)sc, // Data passed to ISR
+ (cyg_ISR_t *)fcc_eth_isr,
+ (cyg_DSR_t *)eth_drv_dsr,
+ &qi->fcc_eth_interrupt_handle,
+ &qi->fcc_eth_interrupt);
+ cyg_drv_interrupt_attach(qi->fcc_eth_interrupt_handle);
+ cyg_drv_interrupt_acknowledge(qi->int_vector);
+ cyg_drv_interrupt_unmask(qi->int_vector);
+#else
+
+ // Mask the interrupts
+ qi->fcc_reg->fcc_fccm = 0;
+#endif
+
+ // Issue Init RX & TX Parameters Command for FCCx
+ while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
+ IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
+ fcc_chan |
+ CPCR_MCN_FCC |
+ CPCR_FLG; /* ISSUE COMMAND */
+ while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
+
+#ifdef CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
+ {
+ unsigned short phy_state;
+ unsigned short reset_mode;
+ int phy_unit = 0;
+ int phy_ok;
+ int phy_timeout = 5*100;
+
+ // Reset PHY (transceiver)
+ _eth_phy_init(qi->phy);
+
+ if (_eth_phy_read(qi->phy, PHY_BMSR, phy_unit, &phy_state)) {
+ if ((phy_state & PHY_BMSR_LINK) != PHY_BMSR_LINK) {
+ _eth_phy_write(qi->phy, PHY_BMCR, phy_unit, PHY_BMCR_RESET);
+ for (i = 0; i < 10; i++) {
+ phy_ok = _eth_phy_read(qi->phy, PHY_BMCR, phy_unit, &phy_state);
+ if (!phy_ok) break;
+ if (!(phy_state & PHY_BMCR_RESET)) break;
+ }
+ if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
+ diag_printf("%s: Can't get PHY unit to soft reset: %x\n", dtp->name, phy_state);
+ return false;
+ }
+ reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG | PHY_BMCR_FULL_DUPLEX;
+ _eth_phy_write(qi->phy, PHY_BMCR, phy_unit, reset_mode);
+ while (phy_timeout-- >= 0) {
+ phy_ok = _eth_phy_read(qi->phy, PHY_BMSR, phy_unit, &phy_state);
+ if (phy_ok && (phy_state & PHY_BMSR_LINK)) {
+ break;
+ } else {
+ CYGACC_CALL_IF_DELAY_US(10000); // 10ms
+ }
+ }
+ if (phy_timeout <= 0) {
+ diag_printf("** %s Warning: PHY LINK UP failed\n", dtp->name);
+ }
+ }
+ else {
+ diag_printf("** %s Info: PHY LINK already UP \n", dtp->name);
+ }
+ }
+ }
+#endif // CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
+
+ // Initialize upper level driver for ecos
+ (sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
+
+ return true;
+}
+
+//
+// This function is called to "start up" the interface. It may be called
+// multiple times, even when the hardware is already running. It will be
+// called whenever something "hardware oriented" changes and should leave
+// the hardware ready to send/receive packets.
+//
+static void
+fcc_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+
+ // Enable the device :
+ // Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive
+ qi->fcc_reg->fcc_gfmr |= (FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
+
+}
+
+//
+// This function is called to shut down the interface.
+//
+static void
+fcc_eth_stop(struct eth_drv_sc *sc)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+
+ // Disable the device :
+ // Clear the ENT/ENR bits in the GFMR -- Disable Transmit/Receive
+ qi->fcc_reg->fcc_gfmr &= ~(FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
+}
+
+
+//
+// This function is called for low level "control" operations
+//
+static int
+fcc_eth_control(struct eth_drv_sc *sc, unsigned long key,
+ void *data, int length)
+{
+ switch (key) {
+ case ETH_DRV_SET_MAC_ADDRESS:
+ return 0;
+ break;
+ default:
+ return 1;
+ break;
+ }
+}
+
+
+//
+// This function is called to see if another packet can be sent.
+// It should return the number of packets which can be handled.
+// Zero should be returned if the interface is busy and can not send any more.
+//
+static int
+fcc_eth_can_send(struct eth_drv_sc *sc)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ volatile struct fcc_bd *txbd = qi->txbd;
+#ifndef FCC_BDs_NONCACHED
+ int cache_state;
+#endif
+
+#ifndef FCC_BDs_NONCACHED
+ HAL_DCACHE_IS_ENABLED(cache_state);
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fcc_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+ }
+#endif
+
+ return ((txbd->ctrl & FCC_BD_Tx_Ready) == 0);
+}
+
+//
+// This routine is called to send data to the hardware.
+static void
+fcc_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
+ int total_len, unsigned long key)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ struct fcc_bd *txbd, *txfirst;
+ volatile char *bp;
+ int i, txindex;
+ int cache_state;
+
+ HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FCC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fcc_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+ }
+#endif
+
+ // Find a free buffer
+ txbd = txfirst = qi->txbd;
+ while (txbd->ctrl & FCC_BD_Tx_Ready) {
+ // This buffer is busy, move to next one
+ if (txbd->ctrl & FCC_BD_Tx_Wrap) {
+ txbd = qi->tbase;
+ } else {
+ txbd++;
+ }
+ if (txbd == txfirst) {
+#ifdef CYGPKG_NET
+ panic ("No free xmit buffers");
+#else
+ os_printf("FCC Ethernet: No free xmit buffers\n");
+#endif
+ }
+ }
+
+ // Remember the next buffer to try
+ if (txbd->ctrl & FCC_BD_Tx_Wrap) {
+ qi->txbd = qi->tbase;
+ } else {
+ qi->txbd = txbd+1;
+ }
+
+ txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
+ qi->txkey[txindex] = key;
+
+ // Set up buffer
+ txbd->length = total_len;
+ bp = txbd->buffer;
+ for (i = 0; i < sg_len; i++) {
+ memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
+ bp += sg_list[i].len;
+ }
+
+ // Make sure no stale data buffer ...
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(txbd->buffer, txbd->length);
+ }
+
+ // Send it on it's way
+ txbd->ctrl |= FCC_BD_Tx_Ready | FCC_BD_Tx_Last | FCC_BD_Tx_TC;
+
+#ifndef FCC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(fcc_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+ }
+#endif
+
+}
+
+//
+// This function is called when a packet has been received. It's job is
+// to prepare to unload the packet from the hardware. Once the length of
+// the packet is known, the upper layer of the driver can be told. When
+// the upper layer is ready to unload the packet, the internal function
+// 'fcc_eth_recv' will be called to actually fetch it from the hardware.
+//
+static void
+fcc_eth_RxEvent(struct eth_drv_sc *sc)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ struct fcc_bd *rxbd;
+ int cache_state;
+
+ HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FCC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fcc_eth_rxring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM);
+ }
+#endif
+
+ rxbd = qi->rnext;
+ while ((rxbd->ctrl & FCC_BD_Rx_Empty) == 0) {
+ qi->rxbd = rxbd; // Save for callback
+
+ // This is the right way of doing it, but dcbi has a bug ...
+ // if (cache_state) {
+ // HAL_DCACHE_INVALIDATE(rxbd->buffer, rxbd->length);
+ // }
+ (sc->funs->eth_drv->recv)(sc, rxbd->length);
+#if 1 // Coherent caches?
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(rxbd->buffer, rxbd->length);
+ }
+#endif
+ rxbd->ctrl |= FCC_BD_Rx_Empty;
+ if (rxbd->ctrl & FCC_BD_Rx_Wrap) {
+ rxbd = qi->rbase;
+ } else {
+ rxbd++;
+ }
+ }
+ // Remember where we left off
+ qi->rnext = (struct fcc_bd *)rxbd;
+
+ // Make sure no stale data
+#ifndef FCC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(fcc_eth_rxring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM);
+ }
+#endif
+
+}
+
+//
+// This function is called as a result of the "eth_drv_recv()" call above.
+// It's job is to actually fetch data for a packet from the hardware once
+// memory buffers have been allocated for the packet. Note that the buffers
+// may come in pieces, using a scatter-gather list. This allows for more
+// efficient processing in the upper layers of the stack.
+//
+static void
+fcc_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ unsigned char *bp;
+ int i;
+
+ bp = (unsigned char *)qi->rxbd->buffer;
+
+ for (i = 0; i < sg_len; i++) {
+ if (sg_list[i].buf != 0) {
+ memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
+ bp += sg_list[i].len;
+ }
+ }
+
+}
+
+static void
+fcc_eth_TxEvent(struct eth_drv_sc *sc, int stat)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ struct fcc_bd *txbd;
+ int txindex;
+#ifndef FCC_BDs_NONCACHED
+ int cache_state;
+#endif
+
+#ifndef FCC_BDs_NONCACHED
+ // Make sure no stale data
+ HAL_DCACHE_IS_ENABLED(cache_state);
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fcc_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+ }
+#endif
+
+ txbd = qi->tnext;
+ // Note: TC field is used to indicate the buffer has/had data in it
+ while ( (txbd->ctrl & (FCC_BD_Tx_TC | FCC_BD_Tx_Ready)) == FCC_BD_Tx_TC ) {
+ if ((txbd->ctrl & FCC_BD_Tx_ERRORS) != 0) {
+#if 0
+ diag_printf("FCC Tx error BD: %x/%x- ", txbd, txbd->ctrl);
+ if ((txbd->ctrl & FCC_BD_Tx_LC) != 0) diag_printf("Late Collision/");
+ if ((txbd->ctrl & FCC_BD_Tx_RL) != 0) diag_printf("Retry limit/");
+// if ((txbd->ctrl & FCC_BD_Tx_RC) != 0) diag_printf("Late Collision/");
+ if ((txbd->ctrl & FCC_BD_Tx_UN) != 0) diag_printf("Underrun/");
+ if ((txbd->ctrl & FCC_BD_Tx_CSL) != 0) diag_printf("Carrier Lost/");
+ diag_printf("\n");
+#endif
+ }
+
+ txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
+ (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
+ txbd->ctrl &= ~FCC_BD_Tx_TC;
+ if (txbd->ctrl & FCC_BD_Tx_Wrap) {
+ txbd = qi->tbase;
+ } else {
+ txbd++;
+ }
+ }
+ // Remember where we left off
+ qi->tnext = (struct fcc_bd *)txbd;
+
+ // Make sure no stale data
+#ifndef FCC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(fcc_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM);
+ }
+#endif
+
+}
+
+//
+// Interrupt processing
+//
+static void
+fcc_eth_int(struct eth_drv_sc *sc)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ unsigned short iEvent;
+
+ while ((iEvent = qi->fcc_reg->fcc_fcce) != 0){
+ // Clear pending interrupts (writing 1's to this register)
+ qi->fcc_reg->fcc_fcce = iEvent;
+ // Tx Done or Tx Error
+ if ( iEvent & (FCC_EV_TXB | FCC_EV_TXE) ) {
+ fcc_eth_TxEvent(sc, iEvent);
+ }
+ // Complete or non-complete frame receive
+ if (iEvent & (FCC_EV_RXF | FCC_EV_RXB) ) {
+ fcc_eth_RxEvent(sc);
+ }
+ }
+}
+
+//
+// Interrupt vector
+//
+static int
+fcc_eth_int_vector(struct eth_drv_sc *sc)
+{
+ struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
+ return (qi->int_vector);
+}
+
Index: devs/eth/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.20
diff -u -5 -p -r1.20 ChangeLog
--- devs/eth/powerpc/quicc/current/ChangeLog 15 Jul 2003 00:57:45 -0000 1.20
+++ devs/eth/powerpc/quicc/current/ChangeLog 19 Aug 2003 16:16:03 -0000
@@ -1,5 +1,10 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * src/if_quicc.c (quicc_eth_init): Use 'quicc_eth_command()'
+ function instead of brute-force inline code.
+
2003-07-14 Gary Thomas <gary@mlbassoc.com>
* src/if_quicc.c (quicc_eth_init): Only flush cache if enabled.
* cdl/quicc_eth_drivers.cdl: Force serial debug messages during
Index: devs/eth/powerpc/quicc/current/src/if_quicc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c,v
retrieving revision 1.20
diff -u -5 -p -r1.20 if_quicc.c
--- devs/eth/powerpc/quicc/current/src/if_quicc.c 15 Jul 2003 00:57:45 -0000 1.20
+++ devs/eth/powerpc/quicc/current/src/if_quicc.c 15 Jul 2003 14:12:35 -0000
@@ -157,10 +157,11 @@ clear_led(int bit)
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
static cyg_interrupt quicc_eth_interrupt;
static cyg_handle_t quicc_eth_interrupt_handle;
#endif
static void quicc_eth_int(struct eth_drv_sc *data);
+static void quicc_eth_command(struct eth_drv_sc *sc, unsigned long cmd);
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// This ISR is called when the ethernet interrupt occurs
static int
quicc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
@@ -364,12 +365,11 @@ quicc_eth_init(struct cyg_netdevtab_entr
enet_pram->taddr_h = 0;
enet_pram->taddr_m = 0;
enet_pram->taddr_l = 0;
// Initialize the CPM (set up buffer pointers, etc).
- eppc->cp_cr = QUICC_CPM_SCCx | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
- while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
+ quicc_eth_command(sc, QUICC_CPM_CR_INIT_TXRX);
// Clear any pending interrupt/exceptions
scc->scc_scce = 0xFFFF;
// Enable interrupts
@@ -707,18 +707,16 @@ quicc_eth_recv(struct eth_drv_sc *sc, st
else
qi->rx_resource++;
}
-
static void
quicc_eth_command( struct eth_drv_sc *sc, unsigned long cmd)
{
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
eppc->cp_cr = QUICC_CPM_SCCx | cmd | QUICC_CPM_CR_BUSY;
-
while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
continue;
}
static void
Index: devs/eth/powerpc/rattler/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/rattler/current/ChangeLog
diff -N devs/eth/powerpc/rattler/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/rattler/current/ChangeLog 19 Aug 2003 16:36:13 -0000
@@ -0,0 +1,44 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * include/rattler_eth.inl:
+ * cdl/rattler_eth_drivers.cdl: New file(s) - platform specifics
+ for ethernet drivers on Analogue & Micro Rattler (MPC8250) board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+
+
Index: devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
diff -N devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/rattler/current/cdl/rattler_eth_drivers.cdl 19 Aug 2003 16:35:47 -0000
@@ -0,0 +1,92 @@
+#====================================================================
+#
+# rattler_eth_drivers.cdl
+#
+# Hardware specifics for A&M Rattler ethernet
+#
+#====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas, hmt
+# Original data: gthomas
+# Contributors: gthomas, F.Robbins
+# Date: 2003-08-19
+#
+#####DESCRIPTIONEND####
+#
+#====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_RATTLER {
+ display "A&M Rattler (MPC8250) ethernet support"
+ description "Hardware specifics for A&M Rattler ethernet"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_HAL_POWERPC
+ active_if CYGPKG_HAL_POWERPC_MPC8XXX
+
+ requires CYGPKG_DEVS_ETH_POWERPC_FCC
+ requires CYGPKG_HAL_POWERPC_RATTLER
+
+ cdl_option CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1 {
+ display "Include fcc1/eth0 ethernet device"
+ default_value 1
+ description "
+ This option controls whether a driver for FCC1/eth0
+ is included in the resulting system."
+ implements CYGHWR_NET_DRIVERS
+ implements CYGHWR_NET_DRIVER_ETH0
+ }
+
+ cdl_option CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC2 {
+ display "Include fcc2/eth1 ethernet device"
+ default_value 1
+ description "
+ This option controls whether a driver for FCC2/eth1
+ is included in the resulting system."
+ implements CYGHWR_NET_DRIVERS
+ implements CYGHWR_NET_DRIVER_ETH1
+ requires CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1
+ }
+
+ include_dir cyg/io
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGDAT_DEVS_FCC_ETH_CDL <pkgconf/devs_eth_powerpc_rattler.h>"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_FCC_ETH_INL <cyg/io/rattler_eth.inl>"
+ }
+}
Index: devs/eth/powerpc/rattler/current/include/rattler_eth.inl
===================================================================
RCS file: devs/eth/powerpc/rattler/current/include/rattler_eth.inl
diff -N devs/eth/powerpc/rattler/current/include/rattler_eth.inl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/rattler/current/include/rattler_eth.inl 19 Aug 2003 16:36:14 -0000
@@ -0,0 +1,311 @@
+#ifndef CYGONCE_DEVS_RATTLER_ETH_INL
+#define CYGONCE_DEVS_RATTLER_ETH_INL
+//==========================================================================
+//
+// rattler_eth.inl
+//
+// Hardware specifics for A&M Rattler ethernet support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas,F.Robbins
+// Date: 2003-08-19
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+//
+// Pin layout for PHY connections
+//
+#define FCC1_PHY_RESET 0x01000000
+#define FCC1_PHY_DATA 0x10000000
+#define FCC1_PHY_CLOCK 0x20000000
+#define FCC2_PHY_RESET 0x02000000
+#define FCC2_PHY_DATA 0x04000000
+#define FCC2_PHY_CLOCK 0x08000000
+
+#ifdef CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1
+//
+// Initialize the PHY associated with FCC1/eth0
+//
+static void
+fcc1_phy_init(void)
+{
+ // Set up PHY reset line
+ IMM->io_regs[PORT_B].pdat &= ~FCC1_PHY_RESET;
+ IMM->io_regs[PORT_B].pdat |= FCC1_PHY_RESET;
+ IMM->io_regs[PORT_C].pdir |= FCC1_PHY_CLOCK;
+}
+
+//
+// Set up a particular data bit for FCC1/eth0
+//
+static void
+fcc1_phy_set_data(int val)
+{
+ if (val) {
+ // Output
+ IMM->io_regs[PORT_C].pdat |= FCC1_PHY_DATA;
+ } else {
+ // Input
+ IMM->io_regs[PORT_C].pdat &= ~FCC1_PHY_DATA;
+ }
+}
+
+//
+// Read the current data bit for FCC1/eth0
+//
+static int
+fcc1_phy_get_data(void)
+{
+ if ((IMM->io_regs[PORT_C].pdat & FCC1_PHY_DATA) != 0) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+//
+// Set the clock bit for FCC1/eth0
+//
+static void
+fcc1_phy_set_clock(int val)
+{
+ if (val) {
+ // Output
+ IMM->io_regs[PORT_C].pdat |= FCC1_PHY_CLOCK;
+ } else {
+ // Input
+ IMM->io_regs[PORT_C].pdat &= ~FCC1_PHY_CLOCK;
+ }
+}
+
+//
+// Set the clock/data direction for FCC1/eth0
+// Note: always forces clock to be an output
+//
+static void
+fcc1_phy_set_dir(int data_dir)
+{
+ if (data_dir) {
+ // Output
+ IMM->io_regs[PORT_C].pdir |= FCC1_PHY_DATA;
+ } else {
+ // Input
+ IMM->io_regs[PORT_C].pdir &= ~FCC1_PHY_DATA;
+ }
+}
+
+ETH_PHY_ACCESS_FUNS(fcc1_phy,
+ fcc1_phy_init,
+ fcc1_phy_set_data,
+ fcc1_phy_get_data,
+ fcc1_phy_set_clock,
+ fcc1_phy_set_dir);
+
+static unsigned char fcc_eth0_rxbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM *
+ (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+static unsigned char fcc_eth0_txbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM *
+ (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+RedBoot_config_option("FCC1/eth0 Network hardware address [MAC]",
+ fcc1_esa,
+ ALWAYS_ENABLED, true,
+ CONFIG_ESA, 0
+ );
+#endif
+
+static struct fcc_eth_info fcc_eth0_info = {
+ CYGNUM_HAL_INTERRUPT_FCC1, // Interrupt
+ "fcc1_esa", // ESA 'key'
+ { 0x00, 0x08, 0xe5, 0x11, 0x22, 0x33 }, // Fallback ESA
+ CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM, // Number of Rx buffers
+ fcc_eth0_rxbufs, // Pointer to buffers
+ CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM, // Number of Tx buffers
+ fcc_eth0_txbufs, // Pointer to buffers
+ &fcc1_phy,
+};
+
+ETH_DRV_SC(fcc_eth0_sc,
+ &fcc_eth0_info, // Driver specific data
+ "eth0", // Name for this interface
+ fcc_eth_start,
+ fcc_eth_stop,
+ fcc_eth_control,
+ fcc_eth_can_send,
+ fcc_eth_send,
+ fcc_eth_recv,
+ fcc_eth_deliver,
+ fcc_eth_int,
+ fcc_eth_int_vector);
+
+NETDEVTAB_ENTRY(fcc_eth0_netdev,
+ "fcc_eth0",
+ fcc_eth_init,
+ &fcc_eth0_sc);
+#endif // CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC1
+
+#ifdef CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC2
+//
+// Initialize the PHY associated with FCC2/eth1
+//
+static void
+fcc2_phy_init(void)
+{
+ // Set up PHY reset line
+ IMM->io_regs[PORT_B].pdat &= ~FCC2_PHY_RESET;
+ IMM->io_regs[PORT_B].pdat |= FCC2_PHY_RESET;
+ IMM->io_regs[PORT_C].pdir |= FCC2_PHY_CLOCK;
+}
+
+//
+// Set up a particular data bit for FCC2/eth1
+//
+static void
+fcc2_phy_set_data(int val)
+{
+ if (val) {
+ // Output
+ IMM->io_regs[PORT_C].pdat |= FCC2_PHY_DATA;
+ } else {
+ // Input
+ IMM->io_regs[PORT_C].pdat &= ~FCC2_PHY_DATA;
+ }
+}
+
+//
+// Read the current data bit for FCC2/eth1
+//
+static int
+fcc2_phy_get_data(void)
+{
+ if ((IMM->io_regs[PORT_C].pdat & FCC2_PHY_DATA) != 0) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+//
+// Set the clock bit for FCC2/eth1
+//
+static void
+fcc2_phy_set_clock(int val)
+{
+ if (val) {
+ // Output
+ IMM->io_regs[PORT_C].pdat |= FCC2_PHY_CLOCK;
+ } else {
+ // Input
+ IMM->io_regs[PORT_C].pdat &= ~FCC2_PHY_CLOCK;
+ }
+}
+
+//
+// Set the clock/data direction for FCC2/eth1
+// Note: always forces clock to be an output
+//
+static void
+fcc2_phy_set_dir(int data_dir)
+{
+ if (data_dir) {
+ // Output
+ IMM->io_regs[PORT_C].pdir |= FCC2_PHY_DATA;
+ } else {
+ // Input
+ IMM->io_regs[PORT_C].pdir &= ~FCC2_PHY_DATA;
+ }
+}
+
+ETH_PHY_ACCESS_FUNS(fcc2_phy,
+ fcc2_phy_init,
+ fcc2_phy_set_data,
+ fcc2_phy_get_data,
+ fcc2_phy_set_clock,
+ fcc2_phy_set_dir);
+
+static unsigned char fcc_eth1_rxbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM *
+ (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+static unsigned char fcc_eth1_txbufs[CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM *
+ (CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE + 32)];
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+RedBoot_config_option("FCC2/eth1 Network hardware address [MAC]",
+ fcc2_esa,
+ ALWAYS_ENABLED, true,
+ CONFIG_ESA, 0
+ );
+#endif
+
+static struct fcc_eth_info fcc_eth1_info = {
+ CYGNUM_HAL_INTERRUPT_FCC2, // Interrupt
+ "fcc2_esa", // ESA 'key'
+ { 0x00, 0x08, 0xe5, 0x11, 0x22, 0x33 }, // Fallback ESA
+ CYGNUM_DEVS_ETH_POWERPC_FCC_RxNUM, // Number of Rx buffers
+ fcc_eth1_rxbufs, // Pointer to buffers
+ CYGNUM_DEVS_ETH_POWERPC_FCC_TxNUM, // Number of Tx buffers
+ fcc_eth1_txbufs, // Pointer to buffers
+ &fcc2_phy,
+};
+
+ETH_DRV_SC(fcc_eth1_sc,
+ &fcc_eth1_info, // Driver specific data
+ "eth1", // Name for this interface
+ fcc_eth_start,
+ fcc_eth_stop,
+ fcc_eth_control,
+ fcc_eth_can_send,
+ fcc_eth_send,
+ fcc_eth_recv,
+ fcc_eth_deliver,
+ fcc_eth_int,
+ fcc_eth_int_vector);
+
+NETDEVTAB_ENTRY(fcc_eth1_netdev,
+ "fcc_eth1",
+ fcc_eth_init,
+ &fcc_eth1_sc);
+#endif // CYGHWR_DEVS_ETH_POWERPC_RATTLER_FCC2
+
+#endif // CYGONCE_DEVS_RATTLER_ETH_INL
+// ------------------------------------------------------------------------
Index: devs/flash/powerpc/rattler/current/ChangeLog
===================================================================
RCS file: devs/flash/powerpc/rattler/current/ChangeLog
diff -N devs/flash/powerpc/rattler/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/rattler/current/ChangeLog 19 Aug 2003 16:38:11 -0000
@@ -0,0 +1,41 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * src/rattler_flash.c:
+ * cdl/flash_rattler.cdl: New file(s) - platform support for
+ FLASH on Analogue & Micro Rattler (MPC8250) boards.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl
===================================================================
RCS file: devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl
diff -N devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/rattler/current/cdl/flash_rattler.cdl 19 Aug 2003 16:37:15 -0000
@@ -0,0 +1,75 @@
+# ====================================================================
+#
+# flash_rattler.cdl
+#
+# FLASH memory - Hardware support on A&M Rattler (MPC8250)
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data: gthomas
+# Contributors:
+# Date: 2003-08-19
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_POWERPC_RATTLER {
+ display "A&M Rattler (MPC8250) FLASH memory support"
+
+ parent CYGPKG_IO_FLASH
+ active_if CYGPKG_IO_FLASH
+ requires CYGPKG_HAL_POWERPC_RATTLER
+
+ implements CYGHWR_IO_FLASH_DEVICE
+
+ compile rattler_flash.c
+
+ # Arguably this should do in the generic package
+ # but then there is a logic loop so you can never enable it.
+ cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED {
+ display "Generic AMD flash driver required"
+ }
+
+ implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
+ requires CYGHWR_DEVS_FLASH_AMD_AM29LV320D
+ requires CYGHWR_DEVS_FLASH_AMD_AM29LV640
+
+}
+
Index: devs/flash/powerpc/rattler/current/src/rattler_flash.c
===================================================================
RCS file: devs/flash/powerpc/rattler/current/src/rattler_flash.c
diff -N devs/flash/powerpc/rattler/current/src/rattler_flash.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/rattler/current/src/rattler_flash.c 19 Aug 2003 16:38:12 -0000
@@ -0,0 +1,74 @@
+//==========================================================================
+//
+// rattler_flash.c
+//
+// Flash programming support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2003-08-19
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//--------------------------------------------------------------------------
+// Device properties
+
+#define CYGNUM_FLASH_INTERLEAVE (1)
+#define CYGNUM_FLASH_SERIES (1)
+#define CYGNUM_FLASH_WIDTH (16)
+#define CYGNUM_FLASH_BASE (0xFE000000)
+#define CYGNUM_FLASH_16AS8 (0)
+
+//--------------------------------------------------------------------------
+// Platform specific extras
+#define CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT // This feature fails :-(
+
+//--------------------------------------------------------------------------
+// Now include the driver code.
+#include "cyg/io/flash_am29xxxxx.inl"
+
+// ------------------------------------------------------------------------
+// EOF rattler_flash.c
Index: devs/flash/powerpc/viper/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/powerpc/viper/current/ChangeLog,v
retrieving revision 1.7
diff -u -5 -p -r1.7 ChangeLog
--- devs/flash/powerpc/viper/current/ChangeLog 24 Jun 2002 13:10:24 -0000 1.7
+++ devs/flash/powerpc/viper/current/ChangeLog 19 Aug 2003 16:40:27 -0000
@@ -1,5 +1,12 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * src/viper_flash.c: Support new board layout which has 16bit
+ wide FLASH devices.
+
+ * cdl/flash_viper.cdl: Add new 8MB device AM29LV640.
+
2002-06-24 Gary Thomas <gary@chez-thomas.org>
* cdl/flash_viper.cdl: Old devices use AM29LV800 chip.
2002-06-20 Gary Thomas <gary@chez-thomas.org>
Index: devs/flash/powerpc/viper/current/cdl/flash_viper.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/powerpc/viper/current/cdl/flash_viper.cdl,v
retrieving revision 1.6
diff -u -5 -p -r1.6 flash_viper.cdl
--- devs/flash/powerpc/viper/current/cdl/flash_viper.cdl 24 Jun 2002 13:10:27 -0000 1.6
+++ devs/flash/powerpc/viper/current/cdl/flash_viper.cdl 19 Aug 2003 16:18:02 -0000
@@ -7,10 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -66,9 +67,10 @@ cdl_package CYGPKG_DEVS_FLASH_VIPER {
display "Generic AMD flash driver required"
}
implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
requires CYGHWR_DEVS_FLASH_AMD_AM29LV320D
+ requires CYGHWR_DEVS_FLASH_AMD_AM29LV640
requires CYGHWR_DEVS_FLASH_AMD_AM29LV800
}
Index: devs/flash/powerpc/viper/current/src/viper_flash.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/powerpc/viper/current/src/viper_flash.c,v
retrieving revision 1.5
diff -u -5 -p -r1.5 viper_flash.c
--- devs/flash/powerpc/viper/current/src/viper_flash.c 20 Jun 2002 23:08:16 -0000 1.5
+++ devs/flash/powerpc/viper/current/src/viper_flash.c 19 Aug 2003 16:18:30 -0000
@@ -7,10 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -53,17 +54,20 @@
#include <cyg/infra/cyg_type.h>
//--------------------------------------------------------------------------
// Device properties
+#ifdef CYGHWR_HAL_POWERPC_VIPER_I // Old board layout
+#define CYGNUM_FLASH_WIDTH (8)
+#define CYGNUM_FLASH_16AS8 (1)
+#else // New board layout
+#define CYGNUM_FLASH_WIDTH (16)
+#define CYGNUM_FLASH_16AS8 (0)
+#endif
#define CYGNUM_FLASH_INTERLEAVE (1)
#define CYGNUM_FLASH_SERIES (1)
-#define CYGNUM_FLASH_WIDTH (8)
#define CYGNUM_FLASH_BASE (0xFE000000)
-#define CYGNUM_FLASH_16AS8 (1)
-
-//static cyg_uint32 plf_flash_base;
//--------------------------------------------------------------------------
// Platform specific extras
#define CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT // This feature fails :-(
Index: hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl,v
retrieving revision 1.7
diff -u -5 -p -r1.7 hal_powerpc_adder.cdl
--- hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl 24 Jul 2003 20:24:06 -0000 1.7
+++ hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl 19 Aug 2003 14:52:04 -0000
@@ -94,11 +94,11 @@ cdl_package CYGPKG_HAL_POWERPC_ADDER {
description "
Select this model for an Adder with the PPC850 processor."
}
cdl_option CYGHWR_HAL_POWERPC_ADDER_II {
- display "Adder-I with 852T"
+ display "Adder-II with 852T"
requires !CYGHWR_HAL_POWERPC_ADDER_I
requires { CYGHWR_HAL_POWERPC_MPC8XX == "852T" }
default_value 0
implements CYGNUM_HAL_QUICC_SMC1
implements CYGNUM_HAL_QUICC_SCC3
Index: hal/powerpc/arch/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/ChangeLog,v
retrieving revision 1.50
diff -u -5 -p -r1.50 ChangeLog
--- hal/powerpc/arch/current/ChangeLog 6 Aug 2003 17:31:26 -0000 1.50
+++ hal/powerpc/arch/current/ChangeLog 19 Aug 2003 16:21:27 -0000
@@ -1,5 +1,11 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * src/hal_intr.c (hal_IRQ_init): Precalculate clock tick per
+ microsecond (us) ratio to reduce overheads in delay. Without
+ this, delays of small numbers of microseconds were inaccurate.
+
2003-08-06 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
* src/vectors.S (cyg_hal_default_interrupt_vsr): Removed ifdef on
CYGFUN_HAL_COMMON_KERNEL_SUPPORT around call to interrupt_end().
Index: hal/powerpc/arch/current/src/hal_intr.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/src/hal_intr.c,v
retrieving revision 1.11
diff -u -5 -p -r1.11 hal_intr.c
--- hal/powerpc/arch/current/src/hal_intr.c 23 May 2002 23:04:14 -0000 1.11
+++ hal/powerpc/arch/current/src/hal_intr.c 19 Aug 2003 16:21:29 -0000
@@ -7,10 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -53,19 +54,24 @@
#include <pkgconf/hal.h>
#include <cyg/hal/hal_intr.h>
+static unsigned long ticks_per_us;
+
externC void
hal_IRQ_init(void)
{
// No architecture general initialization, but the variant may have
// provided some.
hal_variant_IRQ_init();
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
+
+ // Pre-calculate this factor to avoid the extra calculations on each delay
+ ticks_per_us = ((long long)1 * (CYGNUM_HAL_RTC_PERIOD * 100)) / 1000000;
}
// Delay for some number of useconds.
externC void
hal_delay_us(int us)
@@ -74,11 +80,15 @@ hal_delay_us(int us)
long ticks;
int diff;
// Note: the system constant CYGNUM_HAL_RTC_PERIOD corresponds to 10,000us
// Scale the desired number of microseconds to be a number of decrementer ticks
- ticks = ((long long)us * (CYGNUM_HAL_RTC_PERIOD * 100)) / 1000000;
+ if (ticks_per_us > 0) {
+ ticks = us * ticks_per_us;
+ } else {
+ ticks = ((long long)us * (CYGNUM_HAL_RTC_PERIOD * 100)) / 1000000;
+ }
asm volatile("mfdec %0;" : "=r"(old_dec) : );
while (ticks > 0) {
do {
asm volatile("mfdec %0;" : "=r"(new_dec) : );
} while (old_dec == new_dec);
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.31
diff -u -5 -p -r1.31 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog 15 Jul 2003 00:58:02 -0000 1.31
+++ hal/powerpc/mpc8xx/current/ChangeLog 19 Aug 2003 16:41:51 -0000
@@ -1,5 +1,11 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * src/var_misc.c:
+ * include/var_cache.h:
+ * cdl/hal_powerpc_mpc8xx.cdl: New variant 866T.
+
2003-07-14 Gary Thomas <gary@mlbassoc.com>
* include/var_cache.h: Data cache flush on 850 fails when using
cache SPR commands, so use brute force. This fixes some problems
with network based debugging (RedBoot got lost because of cache
Index: hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl,v
retrieving revision 1.9
diff -u -5 -p -r1.9 hal_powerpc_mpc8xx.cdl
--- hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl 23 Mar 2003 16:22:14 -0000 1.9
+++ hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl 19 Aug 2003 14:52:04 -0000
@@ -103,11 +103,11 @@ cdl_package CYGPKG_HAL_POWERPC_MPC8xx {
}
cdl_component CYGHWR_HAL_POWERPC_MPC8XX {
display "PowerPC 8xx microprocessor family"
flavor data
- legal_values { "823" "850" "852T" "855T" "860" "860T" "862T" "862P" }
+ legal_values { "823" "850" "852T" "855T" "860" "860T" "862T" "862P" "866T" }
default_value "860"
implements CYGINT_HAL_POWERPC_VARIANT
description "
The PowerPC 8xx microprocessor family. These are embedded parts
that in addition to the PowerPC processor core have built in peripherals
Index: hal/powerpc/mpc8xx/current/include/var_cache.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_cache.h,v
retrieving revision 1.6
diff -u -5 -p -r1.6 var_cache.h
--- hal/powerpc/mpc8xx/current/include/var_cache.h 15 Jul 2003 00:58:02 -0000 1.6
+++ hal/powerpc/mpc8xx/current/include/var_cache.h 19 Aug 2003 14:52:04 -0000
@@ -81,10 +81,11 @@
#endif // defined(CYGHWR_HAL_POWERPC_MPC862P)
#if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_866T) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
// Data cache
#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
Index: hal/powerpc/mpc8xx/current/src/var_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/src/var_misc.c,v
retrieving revision 1.15
diff -u -5 -p -r1.15 var_misc.c
--- hal/powerpc/mpc8xx/current/src/var_misc.c 16 Apr 2003 16:04:23 -0000 1.15
+++ hal/powerpc/mpc8xx/current/src/var_misc.c 19 Aug 2003 14:52:04 -0000
@@ -128,10 +128,11 @@ hal_variant_idle_thread_action( cyg_uint
#if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
+ defined(CYGHWR_HAL_POWERPC_MPC8XX_866T) || \
defined(CYGHWR_HAL_POWERPC_MPC8XX_862P)
#define NUM_TLBS 32
#elif defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
#define NUM_TLBS 8
#else
Index: hal/powerpc/mpc8xxx/current/ChangeLog
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/ChangeLog
diff -N hal/powerpc/mpc8xxx/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/ChangeLog 19 Aug 2003 16:51:10 -0000
@@ -0,0 +1,51 @@
+2003-08-19 Gary Thomas <gary@mlbassoc.com>
+
+ * src/variant.S:
+ * src/var_misc.c:
+ * src/var_intr.c:
+ * src/quicc2_diag.c:
+ * src/cpm.c:
+ * include/variant.inc:
+ * include/var_regs.h:
+ * include/var_intr.h:
+ * include/var_cache.h:
+ * include/mpc8xxx.h:
+ * cdl/hal_powerpc_mpc8xxx.cdl: New file(s) - variant support for
+ Motorola MPC8xxx (Power-QUICC2) based systems. Roughly based on
+ previously contributed hal/powerpc/mpc8260 package.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl
diff -N hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/cdl/hal_powerpc_mpc8xxx.cdl 19 Aug 2003 16:44:08 -0000
@@ -0,0 +1,177 @@
+# ====================================================================
+#
+# hal_powerpc_mpc8xxx.cdl
+#
+# PowerPC/MPC8xxx variant architectural HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002, 2003 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): pfine
+# Contributors: jskov, gthomas
+# Date: 2001-12-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_POWERPC_MPC8XXX {
+ display "PowerPC MPC8xxx variant HAL"
+ parent CYGPKG_HAL_POWERPC
+ hardware
+ include_dir cyg/hal
+ define_header hal_powerpc_mpc8xxx.h
+ description "
+ The PowerPC MPC8xxx variant HAL package provides generic support
+ for this processor variant. It is also necessary to
+ select a specific target platform HAL package."
+
+ # Note: This should be sub-variant specific to reduce memory use.
+ define_proc {
+ puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3000)"
+ puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)"
+ }
+
+ implements CYGINT_HAL_POWERPC_VARIANT
+
+ cdl_option CYGHWR_HAL_POWERPC_FPU {
+ display "Variant FPU support"
+ calculated 0
+ }
+
+ cdl_option CYGPKG_HAL_POWERPC_MSBFIRST {
+ display "CPU Variant big-endian"
+ calculated 1
+ }
+
+ define_proc {
+ puts $::cdl_header "#include <pkgconf/hal_powerpc.h>"
+ }
+
+ cdl_interface CYGNUM_HAL_MPC8XXX_SMC1 {
+ display "SMC1 is available for serial I/O"
+ description "
+ This interface indicates that SMC1 can be outfitted as
+ a serial device."
+ }
+
+ cdl_interface CYGNUM_HAL_MPC8XXX_SMC2 {
+ display "SMC2 is available for serial I/O"
+ description "
+ This interface indicates that SMC2 can be outfitted as
+ a serial device."
+ }
+
+ cdl_interface CYGNUM_HAL_MPC8XXX_SCC1 {
+ display "SCC1 is available for serial I/O"
+ description "
+ Port SCC1 is available for serial I/O"
+ }
+
+ cdl_interface CYGNUM_HAL_MPC8XXX_SCC2 {
+ display "SCC2 is available for serial I/O"
+ description "
+ Port SCC2 is available for serial I/O"
+ }
+
+ cdl_interface CYGNUM_HAL_MPC8XXX_SCC3 {
+ display "SCC3 is available for serial I/O"
+ description "
+ Port SCC3 is available for serial I/O"
+ }
+
+ cdl_interface CYGNUM_HAL_MPC8XXX_SCC4 {
+ display "SCC4 is available for serial I/O"
+ description "
+ Port SCC4 is available for serial I/O"
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Baud rate for the HAL diagnostic port"
+ flavor data
+ legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+ 4800 7200 9600 14400 19200 38400 57600 115200 230400
+ }
+ default_value 38400
+ description "
+ This option specifies the default baud rate (speed) for the
+ HAL diagnostic port."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated CYGNUM_HAL_MPC8XXX_SMC1+CYGNUM_HAL_MPC8XXX_SMC2+CYGNUM_HAL_MPC8XXX_SCC1+CYGNUM_HAL_MPC8XXX_SCC2+CYGNUM_HAL_MPC8XXX_SCC3+CYGNUM_HAL_MPC8XXX_SCC4
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The MPC8xxx variants can have many serial ports. This option
+ chooses which port will be used to connect to a host running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option chooses which of the serial ports
+ will be used for diagnostic output."
+ }
+
+ # This option is only used when USE_ROM_MONITOR is enabled - but
+ # it cannot be a sub-option to that option, since the code uses the
+ # definition in a preprocessor comparison.
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL {
+ display "Debug serial port used by ROM monitor"
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option chooses which of the serial ports
+ will be used for GDB debugging."
+ }
+
+ compile var_intr.c var_misc.c variant.S quicc2_diag.c cpm.c
+}
Index: hal/powerpc/mpc8xxx/current/include/mpc8xxx.h
===================================================================
RCS file: hal/powerpc/mpc8xxx/current/include/mpc8xxx.h
diff -N hal/powerpc/mpc8xxx/current/include/mpc8xxx.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/mpc8xxx/current/include/mpc8xxx.h 19 Aug 2003 16:44:45 -0000
@@ -0,0 +1,1243 @@
+#ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
+#define CYGONCE_HAL_PPC_QUICC2_MPC8260_H
+
+//==========================================================================
+//
+// mpc8260.h
+//
+// PowerPC QUICC2 register definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002, 2003 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Red Hat
+// Contributors: hmt, gthomas
+// Date: 1999-06-08
+// Purpose: PowerPC QUICC2 definitions
+// Description: PowerPC QUICC2 definitions
+// Usage: THIS IS NOT AN EXTERNAL API
+// This file is in the include dir to share it between
+// QUICCII serial code and MPC8260 initialization code.
+// #include <cyg/hal/mpc8260.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_regs.h> // For IMM base
+
+#define DPRAM_SMC1_OFFSET 0x2000
+#define DPRAM_SMC2_OFFSET 0x2100
+#define DPRAM_BD_OFFSET 0x2200
+
+/*--------------------------*/
+/* Buffer Descriptor Format */
+/*--------------------------*/
+
+typedef struct BufferDescriptor
+
+{
+ CYG_WORD16 bd_cstatus; /* control and status */
+ CYG_WORD16 bd_length; /* transfer length */
+ volatile CYG_BYTE *bd_addr; /* buffer address */
+
+} BD;
+
+
+/*-------------------------------*/
+/* Buffer Descriptor Ring format */
+/*-------------------------------*/
+
+typedef struct BufferDescRings
+
+{
+ BD RxBD; /* Rx BD ring */
+ BD TxBD; /* Tx BD ring */
+
+} BDRINGS;
+
+#define _Packed
+#define _PackedType __attribute__((packed))
+
+/******************************************************************************
+*
+* PARAMETER RAM (PRAM) FOR EACH PERIPHERAL
+*
+* Each subsection contains protocol-specific PRAM for each peripheral,
+* followed by the PRAM common to all protocols for that peripheral. These
+* structs are used as needed in the main MPC8260 memory map structure. Note
+* that different modes of operation will require the use of different PRAM
+* structs, and that certain structs may overlay and conflict with the use of
+* other PRAM areas. Consult the MPC8260 User Manual for details as to what
+* is unavailable when certain protocols are run on certain peripherals.
+*
+******************************************************************************/
+
+
+
+/*---------------------------------------------------------------------------*/
+/* SERIAL COMMUNICATION CONTROLLER (SCC) */
+/*---------------------------------------------------------------------------*/
+
+/*----------*/
+/* SCC HDLC */
+/*----------*/
+
+typedef _Packed struct
+{
+ CYG_BYTE reserved1[4]; /* Reserved area */
+ CYG_WORD c_mask; /* CRC constant */
+ CYG_WORD c_pres; /* CRC preset */
+ CYG_WORD16 disfc; /* discarded frame counter */
+ CYG_WORD16 crcec; /* CRC error counter */
+ CYG_WORD16 abtsc; /* abort sequence counter */
+ CYG_WORD16 nmarc; /* nonmatching address rx cnt */
+ CYG_WORD16 retrc; /* frame transmission counter. */
+ /* For FCC this area is reserved.*/
+ CYG_WORD16 mflr; /* maximum frame length reg */
+ CYG_WORD16 max_cnt; /* maximum length counter */
+ CYG_WORD16 rfthr; /* received frames threshold */
+ CYG_WORD16 rfcnt; /* received frames count */
+ CYG_WORD16 hmask; /* user defined frm addr mask */
+ CYG_WORD16 haddr1; /* user defined frm address 1 */
+ CYG_WORD16 haddr2; /* user defined frm address 2 */
+ CYG_WORD16 haddr3; /* user defined frm address 3 */
+ CYG_WORD16 haddr4; /* user defined frm address 4 */
+ CYG_WORD16 tmp; /* temp */
+ CYG_WORD16 tmp_mb; /* temp */
+} _PackedType t_HdlcScc_Pram;
+
+
+/*--------------*/
+/* SCC Ethernet */
+/*--------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD c_pres; /* CRC preset */
+ CYG_WORD c_mask; /* CRC constant mask*/
+ CYG_WORD crcec; /* CRC error counter */
+ CYG_WORD alec; /* alignment error counter */
+ CYG_WORD disfc; /* discarded frame counter */
+ CYG_WORD16 pads; /* Short frame pad character. */
+ CYG_WORD16 ret_lim; /* Retry limit threshold. */
+ CYG_WORD16 ret_cnt; /* Retry limit counter. */
+ CYG_WORD16 mflr; /* maximum frame length reg */
+ CYG_WORD16 minflr; /* minimum frame length reg */
+ CYG_WORD16 maxd1; /* max DMA1 length register. */
+ CYG_WORD16 maxd2; /* max DMA2 length register. */
+ CYG_WORD16 maxd; /* Rx max DMA. */
+ CYG_WORD16 dma_cnt; /* Rx DMA counter. */
+ CYG_WORD16 max_b; /* max buffer descriptor byte count. */
+ CYG_WORD16 gaddr1; /* group address filter */
+ CYG_WORD16 gaddr2; /* group address filter */
+ CYG_WORD16 gaddr3; /* group address filter */
+ CYG_WORD16 gaddr4; /* group address filter */
+ CYG_WORD tbuf0_data0; /* Saved area 0, current frame. */
+ CYG_WORD tbuf0_data1; /* Saved area 1, current frame. */
+ CYG_WORD tbuf0_rba0;
+ CYG_WORD tbuf0_crc;
+ CYG_WORD16 tbuf0_bcnt;
+ CYG_WORD16 paddr1_h; /* physical address (MSB) */
+ CYG_WORD16 paddr1_m; /* physical address */
+ CYG_WORD16 paddr1_l; /* physical address (LSB) */
+ CYG_WORD16 p_per; /* persistence */
+ CYG_WORD16 rfbd_ptr; /* Rx first BD pointer. */
+ CYG_WORD16 tfbd_ptr; /* Tx first BD pointer. */
+ CYG_WORD16 tlbd_ptr; /* Tx last BD pointer. */
+ CYG_WORD tbuf1_data0; /* Saved area 0, next frame. */
+ CYG_WORD tbuf1_data1; /* Saved area 1, next frame. */
+ CYG_WORD tbuf1_rba0;
+ CYG_WORD tbuf1_crc;
+ CYG_WORD16 tbuf1_bcnt;
+ CYG_WORD16 tx_len; /* tx frame length counter */
+ CYG_WORD16 iaddr1; /* individual address filter. */
+ CYG_WORD16 iaddr2; /* individual address filter. */
+ CYG_WORD16 iaddr3; /* individual address filter. */
+ CYG_WORD16 iaddr4; /* individual address filter. */
+ CYG_WORD16 boff_cnt; /* back-off counter */
+ CYG_WORD16 taddr_h; /* temp address (MSB) */
+ CYG_WORD16 taddr_m; /* temp address */
+ CYG_WORD16 taddr_l; /* temp address (LSB) */
+} _PackedType t_EnetScc_Pram;
+
+/*----------*/
+/* SCC UART */
+/*----------*/
+
+typedef _Packed struct
+{
+ CYG_BYTE reserved1[8]; /* Reserved area */
+ CYG_WORD16 max_idl; /* maximum idle characters */
+ CYG_WORD16 idlc; /* rx idle counter (internal) */
+ CYG_WORD16 brkcr; /* break count register */
+ CYG_WORD16 parec; /* Rx parity error counter */
+ CYG_WORD16 frmec; /* Rx framing error counter */
+ CYG_WORD16 nosec; /* Rx noise counter */
+ CYG_WORD16 brkec; /* Rx break character counter */
+ CYG_WORD16 brkln; /* Receive break length */
+ CYG_WORD16 uaddr1; /* address character 1 */
+ CYG_WORD16 uaddr2; /* address character 2 */
+ CYG_WORD16 rtemp; /* temp storage */
+ CYG_WORD16 toseq; /* Tx out of sequence char */
+ CYG_WORD16 cc[8]; /* Rx control characters */
+ CYG_WORD16 rccm; /* Rx control char mask */
+ CYG_WORD16 rccr; /* Rx control char register */
+ CYG_WORD16 rlbc; /* Receive last break char */
+} _PackedType t_UartScc_Pram;
+
+
+/*-----------------*/
+/* SCC Transparent */
+/*-----------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD c_mask; /* CRC constant */
+ CYG_WORD c_pres; /* CRC preset */
+} _PackedType t_TransScc_Pram;
+
+
+/*------------*/
+/* SCC Bisync */
+/*------------*/
+
+typedef _Packed struct
+{
+ CYG_BYTE reserved1[4]; /* Reserved area */
+ CYG_WORD crcc; /* CRC Constant Temp Value */
+ CYG_WORD16 prcrc; /* Preset Receiver CRC-16/LRC */
+ CYG_WORD16 ptcrc; /* Preset Transmitter CRC-16/LRC */
+ CYG_WORD16 parec; /* Receive Parity Error Counter */
+ CYG_WORD16 bsync; /* BISYNC SYNC Character */
+ CYG_WORD16 bdle; /* BISYNC DLE Character */
+ CYG_WORD16 cc[8]; /* Rx control characters */
+ CYG_WORD16 rccm; /* Receive Control Character Mask */
+} _PackedType t_BisyncScc_Pram;
+
+
+/*-----------------*/
+/* SCC Common PRAM */
+/*-----------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD16 rbase; /* RX BD base address */
+ CYG_WORD16 tbase; /* TX BD base address */
+ CYG_BYTE rfcr; /* Rx function code */
+ CYG_BYTE tfcr; /* Tx function code */
+ CYG_WORD16 mrblr; /* Rx buffer length */
+ CYG_WORD rstate; /* Rx internal state */
+ CYG_WORD rptr; /* Rx internal data pointer */
+ CYG_WORD16 rbptr; /* rb BD Pointer */
+ CYG_WORD16 rcount; /* Rx internal byte count */
+ CYG_WORD rtemp; /* Rx temp */
+ CYG_WORD tstate; /* Tx internal state */
+ CYG_WORD tptr; /* Tx internal data pointer */
+ CYG_WORD16 tbptr; /* Tx BD pointer */
+ CYG_WORD16 tcount; /* Tx byte count */
+ CYG_WORD ttemp; /* Tx temp */
+ CYG_WORD rcrc; /* temp receive CRC */
+ CYG_WORD tcrc; /* temp transmit CRC */
+ union
+ {
+ t_HdlcScc_Pram h;
+ t_EnetScc_Pram e;
+ t_UartScc_Pram u;
+ t_TransScc_Pram t;
+ t_BisyncScc_Pram b;
+ } SpecificProtocol;
+ volatile CYG_BYTE COMPLETE_SIZE_OF_DPRAM_PAGE[0x5c];
+} _PackedType t_Scc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/* FAST COMMUNICATION CONTROLLER (FCC) */
+/*---------------------------------------------------------------------------*/
+
+/*----------*/
+/* FCC HDLC */
+/*----------*/
+
+typedef _Packed struct
+{
+ CYG_BYTE reserved1[8]; /* Reserved area */
+ CYG_WORD c_mask; /* CRC constant */
+ CYG_WORD c_pres; /* CRC preset */
+ CYG_WORD16 disfc; /* discarded frame counter */
+ CYG_WORD16 crcec; /* CRC error counter */
+ CYG_WORD16 abtsc; /* abort sequence counter */
+ CYG_WORD16 nmarc; /* nonmatching address rx cnt */
+ CYG_WORD max_cnt; /* maximum length counter */
+ CYG_WORD16 mflr; /* maximum frame length reg */
+ CYG_WORD16 rfthr; /* received frames threshold */
+ CYG_WORD16 rfcnt; /* received frames count */
+ CYG_WORD16 hmask; /* user defined frm addr mask */
+ CYG_WORD16 haddr1; /* user defined frm address 1 */
+ CYG_WORD16 haddr2; /* user defined frm address 2 */
+ CYG_WORD16 haddr3; /* user defined frm address 3 */
+ CYG_WORD16 haddr4; /* user defined frm address 4 */
+ CYG_WORD16 tmp; /* temp */
+ CYG_WORD16 tmp_mb; /* temp */
+} _PackedType t_HdlcFcc_Pram;
+
+
+/*--------------*/
+/* FCC Ethernet */
+/*--------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD stat_bus; /* Internal use buffer. */
+ CYG_WORD cam_ptr; /* CAM address. */
+ CYG_WORD c_mask; /* CRC constant mask*/
+ CYG_WORD c_pres; /* CRC preset */
+ CYG_WORD crcec; /* CRC error counter */
+ CYG_WORD alec; /* alignment error counter */
+ CYG_WORD disfc; /* discarded frame counter */
+ CYG_WORD16 ret_lim; /* Retry limit threshold. */
+ CYG_WORD16 ret_cnt; /* Retry limit counter. */
+ CYG_WORD16 p_per; /* persistence */
+ CYG_WORD16 boff_cnt; /* back-off counter */
+ CYG_WORD gaddr_h; /* group address filter, high */
+ CYG_WORD gaddr_l; /* group address filter, low */
+ CYG_WORD16 tfcstat; /* out of sequece Tx BD staus. */
+ CYG_WORD16 tfclen; /* out of sequece Tx BD length. */
+ CYG_WORD tfcptr; /* out of sequece Tx BD data pointer. */
+ CYG_WORD16 mflr; /* maximum frame length reg */
+ CYG_WORD16 paddr1_h; /* physical address (MSB) */
+ CYG_WORD16 paddr1_m; /* physical address */
+ CYG_WORD16 paddr1_l; /* physical address (LSB) */
+ CYG_WORD16 ibd_cnt; /* internal BD counter. */
+ CYG_WORD16 ibd_start; /* internal BD start pointer. */
+ CYG_WORD16 ibd_end; /* internal BD end pointer. */
+ CYG_WORD16 tx_len; /* tx frame length counter */
+ CYG_BYTE ibd_base[0x20]; /* internal micro code usage. */
+ CYG_WORD iaddr_h; /* individual address filter, high */
+ CYG_WORD iaddr_l; /* individual address filter, low */
+ CYG_WORD16 minflr; /* minimum frame length reg */
+ CYG_WORD16 taddr_h; /* temp address (MSB) */
+ CYG_WORD16 taddr_m; /* temp address */
+ CYG_WORD16 taddr_l; /* temp address (LSB) */
+ CYG_WORD16 pad_ptr; /* pad_ptr. */
+ CYG_WORD16 cf_type; /* flow control frame type coding. */
+ CYG_WORD16 cf_range; /* flow control frame range. */
+ CYG_WORD16 max_b; /* max buffer descriptor byte count. */
+ CYG_WORD16 maxd1; /* max DMA1 length register. */
+ CYG_WORD16 maxd2; /* max DMA2 length register. */
+ CYG_WORD16 maxd; /* Rx max DMA. */
+ CYG_WORD16 dma_cnt; /* Rx DMA counter. */
+
+ /* counter: */
+ CYG_WORD octc; /* received octets counter. */
+ CYG_WORD colc; /* estimated number of collisions */
+ CYG_WORD broc; /* received good packets of broadcast address */
+ CYG_WORD mulc; /* received good packets of multicast address */
+ CYG_WORD uspc; /* received packets shorter then 64 octets. */
+ CYG_WORD frgc; /* as uspc + bad packets */
+ CYG_WORD ospc; /* received packets longer then 1518 octets. */
+ CYG_WORD jbrc; /* as ospc + bad packets */
+ CYG_WORD p64c; /* received packets of 64 octets.. */
+ CYG_WORD p65c; /* received packets of 65-128 octets.. */
+ CYG_WORD p128c; /* received packets of 128-255 octets.. */
+ CYG_WORD p256c; /* received packets of 256-511 octets.. */
+ CYG_WORD p512c; /* received packets of 512-1023 octets.. */
+ CYG_WORD p1024c; /* received packets of 1024-1518 octets.. */
+ CYG_WORD cam_buf; /* cam respond internal buffer. */
+ CYG_WORD16 rfthr; /* received frames threshold */
+ CYG_WORD16 rfcnt; /* received frames count */
+} _PackedType t_EnetFcc_Pram;
+
+
+/*-----------------*/
+/* FCC Common PRAM */
+/*-----------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD16 riptr; /* Rx internal temporary data pointer. */
+ CYG_WORD16 tiptr; /* Tx internal temporary data pointer. */
+ CYG_WORD16 reserved0; /* Reserved */
+ CYG_WORD16 mrblr; /* Rx buffer length */
+ CYG_WORD rstate; /* Rx internal state */
+ CYG_WORD rbase; /* RX BD base address */
+ CYG_WORD16 rbdstat; /* Rx BD status and control */
+ CYG_WORD16 rbdlen; /* Rx BD data length */
+ CYG_WORD rdptr; /* rx BD data pointer */
+ CYG_WORD tstate; /* Tx internal state */
+ CYG_WORD tbase; /* TX BD base address */
+ CYG_WORD16 tbdstat; /* Tx BD status and control */
+ CYG_WORD16 tbdlen; /* Tx BD data length */
+ CYG_WORD tdptr; /* Tx data pointer */
+ CYG_WORD rbptr; /* rx BD pointer */
+ CYG_WORD tbptr; /* Tx BD pointer */
+ CYG_WORD rcrc; /* Temp receive CRC */
+ CYG_WORD reserved_1[0x1];
+ CYG_WORD tcrc; /* Temp transmit CRC */
+ union /* Protocol-Specific parameter ram */
+ {
+ t_HdlcFcc_Pram h;
+ t_EnetFcc_Pram e;
+ } SpecificProtocol;
+} _PackedType t_Fcc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/* MULTICHANNEL COMMUNICATION CONTROLLER (MCC) */
+/*---------------------------------------------------------------------------*/
+
+/******************************************************************************
+* Note that each MCC uses multiple logical channels. We first define the *
+* PRAM for a logical channel (which can be used in either HDLC or Transparent *
+* mode; wherever there are differences, it is specified), followed by the *
+* PRAM for an MCC itself. *
+******************************************************************************/
+
+/*---------------------*/
+/* MCC Logical Channel */
+/*---------------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD tstate; /* Tx internal state. */
+ CYG_WORD zistate; /* Zero insertion machine state. */
+ CYG_WORD zidata0; /* Zero insertion high CYG_WORD16. */
+ CYG_WORD zidata1; /* Zero insertion low CYG_WORD16. */
+ CYG_WORD16 tbdflags; /* Tx internal BD flags. */
+ CYG_WORD16 tbdcnt; /* Tx internal byte count . */
+ CYG_WORD tbdptr; /* Tx internal data pointer. */
+ CYG_WORD16 intmask; /* Interrupt mask flags. */
+ CYG_WORD16 chamr; /* channel mode register. */
+ CYG_WORD tcrc; /* Transparent: reserved. */
+ /* Hdlc: Temp receive CRC.*/
+ CYG_WORD rstate; /* Rx internal state. */
+ CYG_WORD zdstate; /* Zero deletion machine state. */
+ CYG_WORD zddata0; /* Zero deletion high CYG_WORD16. */
+ CYG_WORD zddata1; /* Zero deletion low CYG_WORD16. */
+ CYG_WORD16 rbdflags; /* Rx internal BD flags. */
+ CYG_WORD16 rbdcnt; /* Rx internal byte count . */
+ CYG_WORD rbdptr; /* Rx internal data pointer. */
+ CYG_WORD16 maxrlen; /* Transparent: Max receive buffer length. */
+ /* Hdlc: Max receive frame length. */
+ CYG_WORD16 sync_maxcnt;/* Transparent: Receive synchronization pattern*/
+ /* Hdlc: Max length counter. */
+ CYG_WORD rcrc; /* Transparent: reserved. */
+ /* Hdlc: Temp receive CRC.*/
+} _PackedType t_Mch_Pram;
+
+
+/*----------*/
+/* MCC PRAM */
+/*----------*/
+
+typedef _Packed struct
+{
+ CYG_WORD mccbase; /* A pointer to starting address of BD rings. */
+ CYG_WORD16 mccstate; /* Controller state. */
+ CYG_WORD16 mrblr; /* Maximum receive buffer length. */
+ CYG_WORD16 grfthr; /* Global receive frame threshold. */
+ CYG_WORD16 grfcnt; /* Global receive frame counter. */
+ CYG_WORD rinttmp; /* Temp location for receive interrupt table entry. */
+ CYG_WORD data0; /* Temporary location for holding data. */
+ CYG_WORD data1; /* Temporary location for holding data. */
+ CYG_WORD tintbase; /* Transmit interrupt table base address. */
+ CYG_WORD tintptr; /* Transmit interrupt table pointer. */
+ CYG_WORD tinttmp; /* Temp location for receive interrupt table entry. */
+ CYG_WORD16 sctpbase; /* A pointer to the super channel transmit table*/
+ CYG_BYTE res0[0x2]; /* Reserved area */
+ CYG_WORD c_mask32; /* CRC constant. */
+ CYG_WORD16 xtrabase; /* A pointer to the beginning of extra parameters */
+ CYG_WORD16 c_mask16; /* CRC constant. */
+ CYG_WORD rinttmp0; /* Temp location for receive interrupt table entry. */
+ CYG_WORD rinttmp1; /* Temp location for receive interrupt table entry. */
+ CYG_WORD rinttmp2; /* Temp location for receive interrupt table entry. */
+ CYG_WORD rinttmp3; /* Temp location for receive interrupt table entry. */
+ CYG_WORD rintbase0; /* Receive interrupt table base address. */
+ CYG_WORD rintptr0; /* Receive interrupt table pointer. */
+ CYG_WORD rintbase1; /* Receive interrupt table base address. */
+ CYG_WORD rintptr1; /* Receive interrupt table pointer. */
+ CYG_WORD rintbase2; /* Receive interrupt table base address. */
+ CYG_WORD rintptr2; /* Receive interrupt table pointer. */
+ CYG_WORD rintbase3; /* Receive interrupt table base address. */
+ CYG_WORD rintptr3; /* Receive interrupt table pointer. */
+ CYG_BYTE pad[0xa0];
+} _PackedType t_Mcc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/* ATM PARAMETER RAM */
+/*---------------------------------------------------------------------------*/
+
+
+/*--------------------------------------*/
+/* Address Compression parameters table */
+/*--------------------------------------*/
+
+_Packed struct AddressCompressionPram
+{
+ volatile CYG_WORD VptBase; /* VP-level addressing table base address */
+ volatile CYG_WORD VctBase; /* VC-level addressing table base address */
+ volatile CYG_WORD Vpt1Base; /* VP1-level addressing table base address */
+ volatile CYG_WORD Vct1Base; /* VC1-level addressing table base address */
+ volatile CYG_WORD16 VpMask; /* VP mask for address compression look-up */
+} _PackedType;
+
+
+/*-------------------------------*/
+/* External CAM parameters table */
+/*-------------------------------*/
+
+_Packed struct ExtCamPram
+{
+ volatile CYG_WORD ExtCamBase; /* Base address of the external CAM */
+ volatile CYG_BYTE reserved00[4]; /* Reserved */
+ volatile CYG_WORD ExtCam1Base; /* Base address of the external CAM1 */
+ volatile CYG_BYTE reserved01[6]; /* Reserved */
+} _PackedType;
+
+
+/*---------------------------*/
+/* ATM mode parameters table */
+/*---------------------------*/
+
+typedef _Packed struct AtmPram
+{
+ volatile CYG_BYTE reserved0[64]; /* Reserved */
+ volatile CYG_WORD16 RxCellTmpBase; /* Rx cell temporary base address */
+ volatile CYG_WORD16 TxCellTmpBase; /* Tx cell temporary base address */
+ volatile CYG_WORD16 UdcTmpBase; /* UDC temp base address (in UDC mode only) */
+ volatile CYG_WORD16 IntRctBase; /* Internal RTC base address */
+ volatile CYG_WORD16 IntTctBase; /* Internal TCT base address */
+ volatile CYG_WORD16 IntTcteBase; /* Internal ACT base address */
+ volatile CYG_BYTE reserved1[4]; /* reserved four bytes */
+ volatile CYG_WORD ExtRctBase; /* Extrnal RTC base address */
+ volatile CYG_WORD ExtTctBase; /* Extrnal TCT base address */
+ volatile CYG_WORD ExtTcteBase; /* Extrnal ACT base address */
+ volatile CYG_WORD16 UeadOffset; /* The offset in half-wordunits of the UEAD
+ entry in the UDC extra header. Should be
+ even address. If little-endian format is
+ used, the UeadOffset is of the little-endian
+ format. */
+ volatile CYG_BYTE reserved2[2]; /* Reserved */
+ volatile CYG_WORD16 PmtBase; /* Performance monitoring table base address */
+ volatile CYG_WORD16 ApcParamBase; /* APC Parameters table base address */
+ volatile CYG_WORD16 FbpParamBase; /* Free buffer pool parameters base address */
+ volatile CYG_WORD16 IntQParamBase; /* Interrupt queue parameters table base */
+ volatile CYG_BYTE reserved3[2];
+ volatile CYG_WORD16 UniStatTableBase; /* UNI statistics table base */
+ volatile CYG_WORD BdBaseExt; /* BD ring base address extension */
+ union
+ {
+ struct AddressCompressionPram AddrCompression;
+ struct ExtCamPram ExtCam;
+ } AddrMapping; /* Address look-up mechanism */
+ volatile CYG_WORD16 VciFiltering; /* VCI filtering enable bits. If bit i is set,
+ the cell with VCI=i will be sent to the
+ raw cell queue. The bits 0-2 and 5 should
+ be zero. */
+ volatile CYG_WORD16 Gmode; /* Global mode */
+ volatile CYG_WORD16 CommInfo1; /* The information field associated with the */
+ volatile CYG_WORD CommInfo2; /* last host command */
+ volatile CYG_BYTE reserved4[4]; /* Reserved */
+ volatile CYG_WORD CRC32Preset; /* Preset for CRC32 */
+ volatile CYG_WORD CRC32Mask; /* Constant mask for CRC32 */
+ volatile CYG_WORD16 AAL1SnpTableBase; /* AAl1 SNP protection look-up table base */
+ volatile CYG_WORD16 reserved5; /* Reserved */
+ volatile CYG_WORD SrtsBase; /* External SRTS logic base address. For AAL1
+ only. Should be 16 bytes aligned */
+ volatile CYG_WORD16 IdleBase; /* Idle cell base address */
+ volatile CYG_WORD16 IdleSize; /* Idle cell size: 52, 56, 60, 64 */
+ volatile CYG_WORD EmptyCellPayload; /* Empty cell payload (little-indian) */
+
+ /* ABR specific only */
+ volatile CYG_WORD Trm; /* Upper bound on time between F-RM cells for active source */
+ volatile CYG_WORD16 Nrm; /* Controls the maximum data cells sent for each F-RM cell. */
+ volatile CYG_WORD16 Mrm; /* Controls bandwidth between F-RM, B-RM and user data cell */
+ volatile CYG_WORD16 Tcr; /* Tag cell rate */
+ volatile CYG_WORD16 AbrRxTcte; /* ABR reserved area address (2-CYG_WORD16 aligned)*/
+ volatile CYG_BYTE reserved7[76]; /* Reserved */
+} _PackedType t_Atm_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/* SERIAL MANAGEMENT CHANNEL (SMC) */
+/*---------------------------------------------------------------------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD16 rbase; /* Rx BD Base Address */
+ CYG_WORD16 tbase; /* Tx BD Base Address */
+ CYG_BYTE rfcr; /* Rx function code */
+ CYG_BYTE tfcr; /* Tx function code */
+ CYG_WORD16 mrblr; /* Rx buffer length */
+ CYG_WORD rstate; /* Rx internal state */
+ CYG_WORD rptr; /* Rx internal data pointer */
+ CYG_WORD16 rbptr; /* rb BD Pointer */
+ CYG_WORD16 rcount; /* Rx internal byte count */
+ CYG_WORD rtemp; /* Rx temp */
+ CYG_WORD tstate; /* Tx internal state */
+ CYG_WORD tptr; /* Tx internal data pointer */
+ CYG_WORD16 tbptr; /* Tx BD pointer */
+ CYG_WORD16 tcount; /* Tx byte count */
+ CYG_WORD ttemp; /* Tx temp */
+
+ /* SMC UART-specific PRAM */
+ CYG_WORD16 max_idl; /* Maximum IDLE Characters */
+ CYG_WORD16 idlc; /* Temporary IDLE Counter */
+ CYG_WORD16 brkln; /* Last Rx Break Length */
+ CYG_WORD16 brkec; /* Rx Break Condition Counter */
+ CYG_WORD16 brkcr; /* Break Count Register (Tx) */
+ CYG_WORD16 r_mask; /* Temporary bit mask */
+
+} _PackedType t_Smc_Pram;
+
+
+
+/*---------------------------------------------------------------------------*/
+/* IDMA PARAMETER RAM */
+/*---------------------------------------------------------------------------*/
+
+typedef _Packed struct
+{
+ CYG_WORD16 ibase; /* IDMA BD Base Address */
+ CYG_WORD16 dcm; /* DMA channel mode register */
+ CYG_WORD16 ibdptr; /* next bd ptr */
+ CYG_WORD16 DPR_buf; /* ptr to internal 64 byte buffer */
+ CYG_WORD16 BUF_inv; /* The quantity of data in DPR_buf */
+ CYG_WORD16 SS_max; /* Steady State Max. transfer size */
+ CYG_WORD16 DPR_in_ptr; /* write ptr for the internal buffer */
+ CYG_WORD16 sts; /* Source Transfer Size */
+ CYG_WORD16 DPR_out_ptr; /* read ptr