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Contributed by Patrick Doyle <wpd@delcomsys.com>
Index: ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ChangeLog,v
retrieving revision 1.88
diff -u -5 -p -r1.88 ChangeLog
--- ChangeLog 10 Dec 2002 15:42:35 -0000 1.88
+++ ChangeLog 12 Dec 2002 20:50:51 -0000
@@ -1,5 +1,11 @@
+2002-12-12 Gary Thomas <gthomas@ecoscentric.com>
+2002-12-12 Patrick Doyle <wpd@delcomsys.com>
+
+ * ecos.db: Add packages for MPC8260 based systems - VADS
+ and TS6 (Delphi Communications).
+
2002-12-10 Gary Thomas <gthomas@ecoscentric.com>
* ecos.db: Enable serial devices for A&M 'adder' platform.
2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
Index: NEWS
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/NEWS,v
retrieving revision 1.58
diff -u -5 -p -r1.58 NEWS
--- NEWS 25 Nov 2002 23:18:41 -0000 1.58
+++ NEWS 12 Dec 2002 20:46:30 -0000
@@ -1,5 +1,7 @@
+* Add support for PowerPC 8260 based systems - one from Motorola (VADS)
+ and another from Delphi Communications. Contributed by Delphi.
* Add support for Analogue & Micro Adder (PowerPC 850) boards
* Update MN10300 ASB2303 HAL to support RedBoot
* New package for application level profiling (histogram only)
* Support for NPWR Linux Engine (Xscale IOP310) from Team ASA
* Support for Allied Telesyn TS1000 (PowerPC 855T based design)
Index: ecos.db
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ecos.db,v
retrieving revision 1.81
diff -u -5 -p -r1.81 ecos.db
--- ecos.db 10 Dec 2002 15:42:35 -0000 1.81
+++ ecos.db 12 Dec 2002 21:06:48 -0000
@@ -451,10 +451,30 @@ package CYGPKG_DEVS_FLASH_MBX {
description "
This package contains hardware support for FLASH memory
on the Motorola PowerPC/860 MBX platform."
}
+package CYGPKG_DEVS_FLASH_TS6 {
+ alias { "FLASH memory support for Delphi Communication Systems, Inc. TigerSHARC6 Board" flash_ts6 }
+ directory devs/flash/powerpc/ts6
+ script flash_ts6.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the Delphi Communication Systems TigerSHARC6 platform."
+}
+
+package CYGPKG_DEVS_FLASH_VADS {
+ alias { "FLASH memory support for Motorola MPC8260 Voyager ADS board" flash_vads }
+ directory devs/flash/powerpc/vads
+ script flash_vads.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the Motorola MPC8260 Voyager ADS platform."
+}
+
package CYGPKG_DEVS_FLASH_CME555 {
alias { "FLASH memory support for Axiom's CME555" flash_cme555 }
directory devs/flash/powerpc/cme555
script flash_cme555.cdl
hardware
@@ -744,10 +764,21 @@ package CYGPKG_IO_SERIAL_POWERPC_QUICC_S
directory devs/serial/powerpc/quicc
script ser_quicc_smc.cdl
description "PowerPC QUICC/SMC serial device drivers"
}
+package CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC {
+ alias { "PowerPC VADS QUICC2/SCC serial device drivers"
+ devs_serial_quicc2_scc quicc2_scc_serial_driver
+ devs_serial_powerpc_quicc2_scc
+ devs_serial_powerpc_quicc2 quicc2_serial_driver }
+ hardware
+ directory devs/serial/powerpc/quicc2
+ script ser_quicc2_scc.cdl
+ description "PowerPC VADS QUICC2/SCC serial device drivers"
+}
+
package CYGPKG_IO_SERIAL_SPARCLITE_SLEB {
alias { "SPARClite SLEB serial device drivers"
devs_serial_sparclite_sleb sleb_serial_driver }
hardware
directory devs/serial/sparclite/sleb
@@ -1187,10 +1218,18 @@ package CYGPKG_DEVS_ETH_POWERPC_MBX {
directory devs/eth/powerpc/mbx
script mbx_eth_drivers.cdl
description "Ethernet driver specifics for Motorola MBX PowerPC (MPC8xx) based boards."
}
+package CYGPKG_DEVS_ETH_POWERPC_QUICC2 {
+ alias { "QUICC2 ethernet driver" quicc_eth_driver }
+ hardware
+ directory devs/eth/powerpc/quicc2
+ script quicc2_eth_drivers.cdl
+ description "Fast ethernet driver for PowerPC QUICC2 (MPC8260) based boards."
+}
+
package CYGPKG_DEVS_ETH_POWERPC_FEC {
alias { "FEC ethernet driver" fec_eth_driver }
hardware
directory devs/eth/powerpc/fec
script fec_eth_drivers.cdl
@@ -2412,10 +2451,21 @@ package CYGPKG_HAL_POWERPC {
support for this processor architecture. It is also necessary to
select a CPU variant and a specific target platform HAL
package."
}
+package CYGPKG_HAL_POWERPC_MPC8260 {
+ alias { "PowerPC MPC8260 variant HAL" hal_mpc8260 }
+ directory hal/powerpc/mpc8260/
+ script hal_powerpc_mpc8260.cdl
+ hardware
+ description "
+ The PowerPC MPC8260 PowerQUICCII variant HAL package provides
+ support for this processor variant. It is also necessary to
+ select a specific target platform HAL package."
+}
+
package CYGPKG_HAL_POWERPC_MPC8xx {
alias { "PowerPC 8xx variant HAL" hal_mpc8xx mpc8xx_hal mpc8xx_arch_hal }
directory hal/powerpc/mpc8xx/
script hal_powerpc_mpc8xx.cdl
hardware
@@ -2525,10 +2575,32 @@ package CYGPKG_HAL_POWERPC_ADDER {
description "
The ADDER HAL package provides the support needed to run
eCos on a A&M ADDER board equipped with a PowerPC processor."
}
+package CYGPKG_HAL_POWERPC_TS6 {
+ alias { "Delphi TigerSHARC-6 board" hal_powerpc_ts6 powerpc_ts6_hal }
+ directory hal/powerpc/ts6
+ script hal_powerpc_ts6.cdl
+ hardware
+ description "
+ The TS6 HAL package provides the support needed to run
+ eCos on a Delphi TigerSHARC-6 board equipped with a
+ PowerPC processor."
+}
+
+package CYGPKG_HAL_POWERPC_VADS {
+ alias { "Motorola MPC8260 VADS board" hal_powerpc_vads powerpc_vads_hal }
+ directory hal/powerpc/vads
+ script hal_powerpc_vads.cdl
+ hardware
+ description "
+ The VADS HAL package provides the support needed to run
+ eCos on a Motorola MPC8260 VADS board equipped with a
+ PowerPC processor."
+}
+
package CYGPKG_HAL_QUICC {
alias { "Motorola MBX860/821 QUICC support" hal_quicc quicc_hal quicc }
directory hal/powerpc/quicc
script hal_powerpc_quicc.cdl
hardware
@@ -3721,10 +3793,40 @@ target mbx {
CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
}
description "
The mbx target provides the packages needed to run
eCos on a Motorola MBX860 or MBX821 board."
+}
+
+target ts6 {
+ alias { "Delphi TigerSHARC-6 board" Pleiades sixpack }
+ packages { CYGPKG_HAL_POWERPC
+ CYGPKG_HAL_POWERPC_MPC8260
+ CYGPKG_HAL_POWERPC_TS6
+ CYGPKG_DEVS_ETH_POWERPC_QUICC2
+ CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
+ CYGPKG_DEVS_FLASH_TS6
+ CYGPKG_DEVS_FLASH_INTEL_28FXXX
+ }
+ description "
+ The ts6 target provides the packages needed to run
+ eCos on a Delphi TigerSHARC-6 board."
+}
+
+target vads {
+ alias { "Motorola MPC8260 VADS board" }
+ packages { CYGPKG_HAL_POWERPC
+ CYGPKG_HAL_POWERPC_MPC8260
+ CYGPKG_HAL_POWERPC_VADS
+ CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
+ CYGPKG_DEVS_ETH_POWERPC_QUICC2
+ CYGPKG_DEVS_FLASH_VADS
+ CYGPKG_DEVS_FLASH_INTEL_28FXXX
+ }
+ description "
+ The vads target provides the packages needed to run
+ eCos on a Motorola MPC8260 VADS board."
}
target viper {
alias { "A&M Viper PPC860 board" viper860 }
packages { CYGPKG_HAL_POWERPC
Index: devs/eth/powerpc/quicc2/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/quicc2/current/ChangeLog
diff -N devs/eth/powerpc/quicc2/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/quicc2/current/ChangeLog 12 Dec 2002 20:52:28 -0000
@@ -0,0 +1,49 @@
+2002-12-12 Gary Thomas <gthomas@ecoscentric.com>
+2002-12-12 Patrick Doyle <wpd@delcomsys.com>
+
+ * src/types.h:
+ * src/if_fec.c:
+ * src/fec.h:
+ * src/EnetPHY.h:
+ * src/EnetPHY.c:
+ * cdl/quicc2_eth_drivers.cdl: New package; ethernet drivers for
+ PowerPC/QUICC2 based systems (like MPC8260).
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+
+
Index: devs/eth/powerpc/quicc2/current/cdl/quicc2_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/quicc2/current/cdl/quicc2_eth_drivers.cdl
diff -N devs/eth/powerpc/quicc2/current/cdl/quicc2_eth_drivers.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/quicc2/current/cdl/quicc2_eth_drivers.cdl 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,115 @@
+# ====================================================================
+#
+# fec_eth_drivers.cdl
+#
+# Ethernet drivers - platform dependent support for PowerPC MPC8260
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): mtek
+# Original data: gthomas
+# Contributors:
+# Date: 2002-02-20
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_QUICC2 {
+ display "MPC8260 FEC ethernet driver"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_HAL_POWERPC
+ active_if CYGPKG_HAL_POWERPC_MPC8260
+
+ implements CYGHWR_NET_DRIVERS
+ implements CYGHWR_NET_DRIVER_ETH0
+ include_dir .
+ include_files ; # none _exported_ whatsoever
+
+ description "Fast ethernet driver for PowerPC MPC8260 boards."
+ compile -library=libextras.a if_fec.c EnetPHY.c
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE {
+ display "Buffer size"
+ flavor data
+ default_value 1540
+ description "
+ This option specifies the size of the internal buffers used
+ for the PowerPC FEC/ethernet device."
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM {
+ display "Number of output buffers"
+ flavor data
+ legal_values 2 to 16
+ default_value 4
+ description "
+ This option specifies the number of output buffer packets
+ to be used for the PowerPC FEC/ethernet device."
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM {
+ display "Number of input buffers"
+ flavor data
+ legal_values 2 to 16
+ default_value 4
+ description "
+ This option specifies the number of input buffer packets
+ to be used for the PowerPC FEC/ethernet device."
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_POWERPC_QUICC2_OPTIONS {
+ display "MPC8260 FEC ethernet driver build options"
+ flavor none
+ no_define
+
+ cdl_option CYGPKG_DEVS_ETH_POWERPC_QUICC2_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "-D_KERNEL -D__ECOS" }
+ description "
+ This option modifies the set of compiler flags for
+ building the MPC8260 FEC ethernet driver package.
+ These flags are used in addition to the set of global
+ flags."
+ }
+ }
+}
Index: devs/eth/powerpc/quicc2/current/src/EnetPHY.c
===================================================================
RCS file: devs/eth/powerpc/quicc2/current/src/EnetPHY.c
diff -N devs/eth/powerpc/quicc2/current/src/EnetPHY.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/quicc2/current/src/EnetPHY.c 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,362 @@
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+/*-------------------------------------------------------------------
+*
+* FILE: enetPHY.c
+*
+* DESCRIPTION: GPIO Management Pins driver for the LXT970a
+*
+*
+* Modified for the mpc8260 VADS board
+*--------------------------------------------------------------------*/
+#include "types.h"
+#include "EnetPHY.h"
+
+/* Internal functions */
+void MdioSend(UINT32, UINT16);
+UINT16 MdioReceive(UINT16);
+UINT16 MdioFrame(MDIORW, UINT16, UINT16, UINT32);
+
+VUINT32 * pPortDir;
+VUINT32 * pPortData;
+
+/*-------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION:
+*
+* EXTERNAL EFFECT: Turns on the LXT970 transciever
+*
+* PARAMETERS:
+*
+* RETURNS: None
+*
+* ASSUMPTIONS:
+*
+*-------------------------------------------------------------------*/
+void
+EnableResetPHY(volatile t_BCSR *pBCSR)
+{
+ // active low FETHIEN on BSCR1, assert reset low
+ pBCSR->bcsr1 &= ~(FETHIEN_ | FETHRST_);
+ // de-assert reset
+ pBCSR->bcsr1 |= FETHRST_;
+
+}
+
+
+/*-------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION: Writes parameters to the control registers of LXT970
+*
+* EXTERNAL EFFECT:
+*
+* PARAMETERS:
+*
+* RETURNS: None
+*
+* ASSUMPTIONS:
+*
+*-------------------------------------------------------------------*/
+UINT16
+InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link)
+{
+
+ VUINT16 FrameValue;
+
+ /* 8101 Ethernet Management Pin Assignments */
+ pPortDir = pdir;
+ pPortData = pdat;
+
+ (*pPortDir) |= MDC_PIN_MASK; /* MD_Clock will always be output only */
+
+ /* Test MDC & MDIO Pin Connection to PHY */
+ MdioFrame(WRITE, 0, MIRROR_REG, MD_TEST_FRAME); //send test frame
+ MdioFrame(WRITE, 0, MIRROR_REG, MD_TEST_FRAME); //send test frame
+ FrameValue = MdioFrame(READ, 0, MIRROR_REG, 0); //read test frame
+
+ if (FrameValue != MD_TEST_FRAME)
+ return LINKERROR; //test data integrity
+
+ /* General Configuration */
+ MdioFrame(WRITE, 0, CONFIG_REG, 0x0000);
+
+ if(link == HUNDRED_HD)
+ MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0081); //100 Mbps Half, 802.3
+ else
+ MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0021); //10 Mbps Half, 802.3
+
+ // 100 Mbps full duplex not supported
+ // MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0101); //100 Mbps Full, 802.3
+
+ MdioFrame(WRITE, 0, CONTROL_REG, 0x1300);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION:
+*
+* EXTERNAL EFFECT:
+*
+* PARAMETERS:
+*
+* RETURNS: None
+*
+* ASSUMPTIONS:
+*
+*-------------------------------------------------------------------*/
+UINT16
+EthernetPHYInterruptHandler()
+{
+ // Reading registers 1 and 18 in sequence
+ // clears the transceiver interrupt
+
+ MdioFrame(READ, 0, STATUS_REG, 0);
+ MdioFrame(READ, 0, INT_STAT_REG, 0);
+
+ return LinkTestPHY();
+} /* end EthernetPHYInterruptHandler */
+
+/*-------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION:
+*
+* EXTERNAL EFFECT:
+*
+* PARAMETERS:
+*
+* RETURNS: None
+*
+* ASSUMPTIONS:
+*
+*-------------------------------------------------------------------*/
+UINT16
+LinkTestPHY()
+{
+ UINT32 j, cnt;
+ UINT16 FrameValue;
+
+ //for (j = 0; j < 10; j++) {
+ for (j = 0; j < 5; j++) {
+
+ for (cnt = 0; cnt < 1000000; cnt ++) {
+
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ }
+
+ FrameValue = MdioFrame(READ,0,CHIP_STAT_REG,0);
+
+ if ( (FrameValue & 0x0200) != 0 )
+ break;
+ }
+
+ FrameValue &= 0x3800;
+
+ switch (FrameValue) {
+
+ case 0x3800: return HUNDRED_FD;
+ case 0x2800: return HUNDRED_HD;
+ case 0x3000: return TEN_FD;
+ case 0x2000: return TEN_HD;
+ default: return NOTLINKED;
+ }
+
+}
+
+/*-------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION:
+*
+* EXTERNAL EFFECT:
+*
+* PARAMETERS:
+*
+* RETURNS: None
+*
+* ASSUMPTIONS:
+*
+*-------------------------------------------------------------------*/
+void EnablePHYinterrupt(UINT8 enable)
+{
+ MdioFrame(WRITE, 0, INT_EN_REG, enable?0x2:0x0);
+}
+
+/*----------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION: generic READ/WRITE function of LXT970
+* through the MDC/MDIO interface.
+*
+* EXTERNAL EFFECT:
+*
+* PARAMETERS:
+*
+* RETURNS: None
+*
+* ASSUMPTIONS:
+*
+*---------------------------------------------------------------------*/
+UINT16
+MdioFrame(MDIORW R_W, UINT16 PhyAddr, UINT16 RegAddr, UINT32 PutData) {
+
+ UINT16 GetData;
+
+ *pPortDir |= MDIO_PIN_MASK; //set to output mode
+
+ MdioSend(0xFFFFFFFF,32); //PreAmble
+ MdioSend(0x1,2); //Start Frame Delimiter
+ if (R_W==READ)
+ MdioSend(0x2,2); //Read OpCode
+ else
+ MdioSend(0x1,2); //Write OpCode
+
+ MdioSend(PhyAddr,5); //Send PHY transciever Address
+ MdioSend(RegAddr,5); //Send Register Address
+
+ if (R_W==READ) {
+ *pPortDir &= ~MDIO_PIN_MASK; //set to input mode
+ GetData = MdioReceive(17); //Drive TurnAround and Data
+ MdioReceive(2);
+ }
+ else {
+ MdioSend(0x2,2); //Drive TurnAround
+ MdioSend(PutData, 16); //Send Data
+ GetData = 0;
+ *pPortDir &= ~MDIO_PIN_MASK; //set to input mode
+ }
+
+ return GetData;
+
+}
+/*----------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION: Shift out bits of data
+*
+* EXTERNAL EFFECT:
+*
+* PARAMETERS:
+*
+* RETURNS: None
+*
+* ASSUMPTIONS:
+*
+*----------------------------------------------------------------------*/
+void
+MdioSend(UINT32 txF, UINT16 size) {
+
+ UINT32 dmask;
+ INT_NATIVE i, j;
+
+ dmask = 1 << (size-1); // msbit out first
+
+ for (i = 0; i < size; i++) { // for "size" bits
+
+ if ( txF & dmask ) //output data bit high
+ *pPortData |= MDIO_PIN_MASK;
+ else //output data bit low > 400ns
+ *pPortData &= ~MDIO_PIN_MASK;
+ // >10ns
+ *pPortData |= MDC_PIN_MASK; // clock rise
+
+ txF = (UINT32)(txF << 1); // >160ns
+
+ for (j=0; j<MDC_HOLD_TIME; j++);
+
+ *pPortData &= ~MDC_PIN_MASK; // clock fall
+
+ for (j=0; j<MDC_HOLD_TIME; j++);
+
+ }
+
+ return;
+}
+
+
+/*---------------------------------------------------------------------
+*
+* FUNCTION NAME:
+*
+* DESCRIPTION: Shifts in bits of data
+*
+* EXTERNAL EFFECT:
+*
+* PARAMETERS:
+*
+* RETURNS:
+*
+* ASSUMPTIONS:
+*
+*---------------------------------------------------------------------*/
+UINT16
+MdioReceive(UINT16 size) {
+
+ UINT16 i,j, rxF = 0;
+
+ for (i = 0; i < size; i++) { // 16 bits
+
+ *pPortData |= MDC_PIN_MASK; // clock rise
+
+ if ( *pPortData & MDIO_PIN_MASK ) // if read in a high bit
+ rxF = ( (UINT16)(rxF << 1) | 1 ); // shift in a one
+ else // if read in a low bit
+ rxF = ( (UINT16)(rxF << 1) & ~(UINT16)1 ); // shift in a zero
+
+
+ for (j=0; j<MDC_HOLD_TIME; j++);
+
+ *pPortData &= ~MDC_PIN_MASK; // clock fall
+
+ for (j=0; j<MDC_HOLD_TIME; j++);
+
+ }
+
+ return rxF;
+}
+
Index: devs/eth/powerpc/quicc2/current/src/EnetPHY.h
===================================================================
RCS file: devs/eth/powerpc/quicc2/current/src/EnetPHY.h
diff -N devs/eth/powerpc/quicc2/current/src/EnetPHY.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/quicc2/current/src/EnetPHY.h 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,111 @@
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+/*------------------------------------------------------------------
+*
+* FILE: EnetPHY.c
+*
+* DESCRIPTION: LXT970a driver header file
+*
+*
+* Modified for MPC8260 VADS board
+*-------------------------------------------------------------------*/
+
+#ifndef _EnetPHY_H
+#define _EnetPHY_H
+
+#include "types.h"
+
+// Board control and status registers
+typedef struct bcsr {
+ UINT32 bcsr0;
+ UINT32 bcsr1;
+ UINT32 bcsr2;
+ UINT32 bcsr3;
+} t_BCSR;
+
+// Fast ethernet enable/reset pins on bcsr
+#define FETHIEN_ 0x08000000
+#define FETHRST_ 0x04000000
+
+
+/**************************/
+/* The API for PHY Device */
+/**************************/
+
+void EnableResetPHY(volatile t_BCSR *pBCSR);
+UINT16 InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link);
+UINT16 EthernetPHYInterruptHandler(void);
+void EnablePHYinterrupt(UINT8 enable);
+UINT16 LinkTestPHY(void);
+
+
+typedef enum MDIORW {READ, WRITE} MDIORW;
+
+
+#define LINKERROR 0xFFFF
+#define NOTLINKED 0x0000
+#define TEN_HD 0x0020
+#define TEN_FD 0x0040
+#define HUNDRED_HD 0x0080
+#define HUNDRED_FD 0x0100
+
+#define MD_TEST_FRAME 0xDEAD
+
+//8260 VADS Pin Connections
+#define MDIO_PIN_MASK 0x00400000 //PC9 for 8260 VADS
+#define MDC_PIN_MASK 0x00200000 //PC10 for 8260 VADS
+
+//#define MDIO_PIN_MASK 0x00000200 //PC9 for 8260 VADS
+//#define MDC_PIN_MASK 0x00000400 //PC10 for 8260 VADS
+
+//IEEE 802.3 PHY Register Definitions
+#define CONTROL_REG 0
+#define STATUS_REG 1
+#define PHY_ID_REG_A 2
+#define PHY_ID_REG_B 3
+#define AUTONEG_AD_REG 4
+#define AUTONEG_LINKPARTNER_REG 5
+#define AUTONEG_EXP_REG 6
+
+//LXT970a Specific Register Definitions
+#define MIRROR_REG 16
+#define INT_EN_REG 17
+#define INT_STAT_REG 18
+#define CONFIG_REG 19
+#define CHIP_STAT_REG 20
+
+//Clock Timing Control
+#define MDC_HOLD_TIME 50
+
+#endif
Index: devs/eth/powerpc/quicc2/current/src/fec.h
===================================================================
RCS file: devs/eth/powerpc/quicc2/current/src/fec.h
diff -N devs/eth/powerpc/quicc2/current/src/fec.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/quicc2/current/src/fec.h 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,173 @@
+//==========================================================================
+//
+// fec.h
+//
+// PowerPC MPC8260 fast ethernet (FEC)
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): mtek
+// Contributors: pfine
+// Date: 2002-02-20
+// Purpose:
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// The port connected to the ethernet
+#define QUICC2_VADS_IMM_BASE 0x04700000
+#define FCC2 1
+
+/* ------------------------ */
+/* FCC REGISTER CONSTANTS */
+/* ------------------------ */
+
+// GFMR masks (RESET: 0x00000000)
+#define FEC_GFMR_EN_Rx 0x00000020 // Receive enable
+#define FEC_GFMR_EN_Tx 0x00000010 // Transmit enable
+#define FEC_GFMR_INIT 0x0000000C // mode=ethernet
+#define FEC_GFMR_OFFSET 0x11320
+
+//PSMR masks (RESET: 0x00000000)
+#define FEC_PSMR_INIT 0x00000080 // 32-bit CRC
+#define FEC_PSMR_OFFSET 0x11324
+
+//TODR masks (RESET: 0x0000)
+#define FEC_TOD_INIT 0x0000
+#define FEC_TOD_SET 0x8000
+#define FEC_TOD_OFFSET 0x11328
+
+//DSR masks (RESET: 0x7E7E)
+#define FEC_DSR_INIT 0xD555
+#define FEC_DSR_OFFSET 0x1132C
+
+//FCCE & FCCM (RESET: 0x0000)
+#define FEC_EV_GRA 0x00800000 // Graceful stop
+#define FEC_EV_RXC 0x00400000 // A control frame has been received
+#define FEC_EV_TXC 0x00200000 // Out of sequence frame sent
+#define FEC_EV_TXE 0x00100000 // Error in transmission channel
+#define FEC_EV_RXF 0x00080000 // A complete frame received
+#define FEC_EV_BSY 0x00040000 // A received frame discarded due to lack
+ // of buffers
+#define FEC_EV_TXB 0x00020000 // A buffer sent to ethernet
+#define FEC_EV_RXB 0x00010000 // A buffer that is a non-complete frame
+ // is received
+#define FEC_FCCE_OFFSET 0x11330
+#define FEC_FCCM_OFFSET 0x11334
+
+/* ------------------------------ */
+/* FCC PARAMETER RAM CONSTANTS */
+/* ------------------------------ */
+
+#define FEC_PRAM_RIPTR 0x3000 // 32 byte buffer in dual port RAM
+#define FEC_PRAM_TIPTR 0xB000 // 32 byte buffer in dual port RAM
+#define FEC_FCR_INIT 0x00000000 // Clear the reserved bits
+#define FEC_FCR_MOT_BO 0x10000000 // Motorola byte ordering
+#define FEC_PRAM_C_MASK 0xDEBB20E3 // Constant MASK for CRC
+#define FEC_PRAM_C_PRES 0xFFFFFFFF // CRC Preset
+#define FEC_PRAM_RETLIM 15 // Retry limit
+#define FEC_PRAM_PER_LO 5 // Persistance
+#define FEC_PRAM_PER_HI 0
+#define FEC_PRAM_MRBLR 1536
+#define FEC_MAX_FLR 1518 // Max frame length
+#define FEC_MIN_FLR 64 // Min frame length
+#define FEC_PRAM_PAD_CH 0x8888
+#define FEC_PRAM_MAXD 1520
+#define FEC_PRAM_OFFSET 0x8500 // Offset of t_Fcc_Pram in 82xx
+
+/* ------------------------------ */
+/* BUFFER DESCRIPTOR CONSTANTS */
+/* ------------------------------ */
+#define FEC_PRAM_RxBD_Base (FEC_PRAM_RIPTR + 0x400)
+#define FEC_BD_Rx_Empty 0x8000 // Buffer is empty, FEC can fill
+#define FEC_BD_Rx_Wrap 0x2000 // Wrap: Last buffer in ring
+#define FEC_BD_Rx_Int 0x1000 // Interrupt
+#define FEC_BD_Rx_Last 0x0800 // Last buffer in frame
+#define FEC_BD_Rx_Miss 0x0100 // Miss: promiscious mode
+#define FEC_BD_Rx_BC 0x0080 // Broadcast address
+#define FEC_BD_Rx_MC 0x0040 // Multicast address
+#define FEC_BD_Rx_LG 0x0020 // Frame length violation
+#define FEC_BD_Rx_NO 0x0010 // Non-octet aligned frame
+#define FEC_BD_Rx_SH 0x0008 // Short frame
+#define FEC_BD_Rx_CR 0x0004 // CRC error
+#define FEC_BD_Rx_OV 0x0002 // Overrun
+#define FEC_BD_Rx_TR 0x0001 // Frame truncated. late collision
+
+#define FEC_PRAM_TxBD_Base (FEC_PRAM_TIPTR + 0x400)
+#define FEC_BD_Tx_Ready 0x8000 // Frame ready
+#define FEC_BD_Tx_Pad 0x4000 // Pad short frames
+#define FEC_BD_Tx_Wrap 0x2000 // Wrap: Last buffer in ring
+#define FEC_BD_Tx_Int 0x1000 // Interrupt
+#define FEC_BD_Tx_Last 0x0800 // Last buffer in frame
+#define FEC_BD_Tx_TC 0x0400 // Send CRC after data
+#define FEC_BD_Tx_DEF 0x0200 // Defer indication
+#define FEC_BD_Tx_HB 0x0100 // Heartbeat
+#define FEC_BD_Tx_LC 0x0080 // Late collision
+#define FEC_BD_Tx_RL 0x0040 // Retransmission limit
+#define FEC_BD_Tx_RC 0x003C // Retry count
+#define FEC_BD_Tx_UN 0x0002 // Underrun
+#define FEC_BD_Tx_CSL 0x0001 // Carrier sense lost
+
+
+// Buffer descriptor
+struct fec_bd {
+ volatile unsigned short ctrl;
+ volatile unsigned short length;
+ volatile unsigned char *buffer;
+};
+
+
+struct fec_eth_info {
+ volatile struct fcc_regs *fcc_reg; // See "mpc8260.h"
+ struct fec_bd *txbd, *rxbd; // Next Tx,Rx descriptor to use
+ struct fec_bd *tbase, *rbase; // First Tx,Rx descriptor
+ struct fec_bd *tnext, *rnext; // Next descriptor to check for interrupt
+ int txsize, rxsize; // Length of individual buffers
+ unsigned long txkey[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM];
+};
+
+// CPM_CPCR masks
+#define CPCR_FLG 0x00010000
+#define CPCR_FCC2_CH 0x16200000
+#define CPCR_GRSTOP_TX 0x00000005
+#define CPCR_INIT_TX_RX_PARAMS 0x00000000
+#define CPCR_MCN_FEC 0x00000300
+#define CPCR_READY_TO_RX_CMD 0 /* Ready to receive a command */
Index: devs/eth/powerpc/quicc2/current/src/if_fec.c
===================================================================
RCS file: devs/eth/powerpc/quicc2/current/src/if_fec.c
diff -N devs/eth/powerpc/quicc2/current/src/if_fec.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/quicc2/current/src/if_fec.c 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,721 @@
+//==========================================================================
+//
+// dev/if_fec.c
+//
+// Fast ethernet device driver for PowerPC MPC8260 boards
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): mtek
+// Contributors: pfine
+// Date: 2002-02-20
+// Purpose:
+// Description: hardware driver for MPC8260 FEC
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/devs_eth_powerpc_quicc2.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_intr.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/mpc8260.h>
+
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#ifdef CYGPKG_NET
+#include <pkgconf/net.h>
+#endif
+
+#include "fec.h"
+#include "EnetPHY.h"
+
+#define ALIGN_TO_CACHE_LINES(x) ( (long)((x) + 31) & 0xffffffe0 )
+
+static unsigned char fec_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM *
+ (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)];
+static unsigned char fec_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM *
+ (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)];
+
+// Buffer descriptors are in dual ported RAM, which is marked non-cached
+#define FEC_BDs_NONCACHED
+static struct fec_bd *const fec_eth_rxring = (struct fec_bd *)
+ (QUICC2_VADS_IMM_BASE + FEC_PRAM_RxBD_Base);
+static struct fec_bd *const fec_eth_txring = (struct fec_bd *)
+ (QUICC2_VADS_IMM_BASE + FEC_PRAM_TxBD_Base);
+
+static struct fec_eth_info fec_eth0_info;
+
+static unsigned short _default_enaddr[] = {0x1234, 0x5678, 0x90a1};
+static unsigned char enaddr[6];
+
+#ifdef CYGPKG_REDBOOT
+#include <pkgconf/redboot.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <redboot.h>
+#include <flash_config.h>
+RedBoot_config_option("Network hardware address [MAC]",
+ fec_esa,
+ ALWAYS_ENABLED, true,
+ CONFIG_ESA, 0
+ );
+RedBoot_config_option("Attempt to find 100 Mbps Ethernet",
+ fec_100,
+ ALWAYS_ENABLED, true,
+ CONFIG_BOOL, 0
+ );
+#endif
+#endif
+
+#define os_printf diag_printf
+
+// CONFIG_ESA and CONFIG_BOOL are defined in redboot/include/flash_config.h
+#ifndef CONFIG_ESA
+#define CONFIG_ESA 6 // ethernet address length ...
+#endif
+
+#ifndef CONFIG_BOOL
+#define CONFIG_BOOL 1
+#endif
+
+ETH_DRV_SC(fec_eth0_sc,
+ &fec_eth0_info, // Driver specific data
+ "eth0", // Name for this interface
+ fec_eth_start,
+ fec_eth_stop,
+ fec_eth_control,
+ fec_eth_can_send,
+ fec_eth_send,
+ fec_eth_recv,
+ fec_eth_deliver,
+ fec_eth_int,
+ fec_eth_int_vector);
+
+NETDEVTAB_ENTRY(fec_netdev,
+ "fec_eth",
+ fec_eth_init,
+ &fec_eth0_sc);
+
+#ifdef CYGPKG_NET
+static cyg_interrupt fec_eth_interrupt;
+static cyg_handle_t fec_eth_interrupt_handle;
+#endif
+static void fec_eth_int(struct eth_drv_sc *data);
+
+#define FEC_ETH_INT CYGNUM_HAL_INTERRUPT_FCC2
+
+// This ISR is called when the ethernet interrupt occurs
+#ifdef CYGPKG_NET
+static int
+fec_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
+{
+ cyg_drv_interrupt_mask(FEC_ETH_INT);
+ return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
+}
+#endif
+
+// Deliver function (ex-DSR) handles the ethernet [logical] processing
+static void
+fec_eth_deliver(struct eth_drv_sc * sc)
+{
+ fec_eth_int(sc);
+#ifdef CYGPKG_NET
+ // Clearing the event register acknowledges FCC2 interrupt ...
+ // cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
+ cyg_drv_interrupt_unmask(FEC_ETH_INT);
+#endif
+
+}
+
+
+// Initialize the interface - performed at system startup
+// This function must set up the interface, including arranging to
+// handle interrupts, etc, so that it may be "started" cheaply later.
+static bool
+fec_eth_init(struct cyg_netdevtab_entry *tab)
+{
+ struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+
+ volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
+ volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET);
+ volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e);
+#ifdef CYGPKG_HAL_POWERPC_VADS
+ volatile t_BCSR *CSR = (t_BCSR *) 0x04500000;
+#endif
+
+ int cache_state;
+ int i;
+ bool esa_ok;
+ bool fec_100;
+ unsigned char *c_ptr;
+ UINT16 link_speed;
+
+ // Ensure consistent state between cache and what the FEC sees
+ HAL_DCACHE_IS_ENABLED(cache_state);
+ if (cache_state) {
+ HAL_DCACHE_DISABLE();
+ HAL_DCACHE_INVALIDATE_ALL();
+ }
+
+ // Link the memory to the driver control memory
+ qi->fcc_reg = & (IMM->fcc_regs[FCC2]);
+
+ // just in case : disable Transmit and Receive
+ qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
+
+ // Via BCSR, (re)start LXT970
+#ifdef CYGPKG_HAL_POWERPC_VADS
+ EnableResetPHY(CSR);
+#endif
+
+ // Try to read the ethernet address of the transciever ...
+#ifdef CYGPKG_REDBOOT
+ esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL);
+#else
+ esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_100", &fec_100, CONFIG_BOOL);
+#endif
+
+ link_speed = NOTLINKED;
+ if(esa_ok && fec_100){
+ // Via MII Management pins, tell LXT970 to initialize
+ os_printf("Attempting to acquire 100 Mbps half_duplex link ...");
+ InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
+ (VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
+ HUNDRED_HD);
+
+ link_speed = LinkTestPHY();
+ os_printf("\n");
+ if(link_speed == NOTLINKED){
+ os_printf("Failed to get 100 Mbps half_duplex link.\n");
+ }
+ }
+ if(link_speed == NOTLINKED){
+ os_printf("Attempting to acquire 10 Mbps half_duplex link ...");
+ InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
+ (VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
+ TEN_HD);
+ link_speed = LinkTestPHY();
+ os_printf("\n");
+ if(link_speed == NOTLINKED){
+ link_speed = LinkTestPHY();
+ os_printf("Failed to get 10 Mbps half_duplex link.\n");
+ }
+
+ }
+ switch ( link_speed ) {
+
+ case HUNDRED_FD:
+ os_printf("100 MB full-duplex ethernet link \n");
+ break;
+ case HUNDRED_HD:
+ os_printf("100 MB half-duplex ethernet link \n");
+ break;
+ case TEN_FD:
+ os_printf("10 MB full-duplex ethernet link \n");
+ break;
+ case TEN_HD:
+ os_printf("10 MB half-duplex ethernet link \n");
+ break;
+ default:
+ os_printf("NO ethernet link \n");
+ }
+
+ // Connect PORTC pins: (C19) to clk13, (C18) to clk 14
+ IMM->io_regs[PORT_C].ppar |= 0x00003000;
+ IMM->io_regs[PORT_C].podr &= ~(0x00003000);
+ IMM->io_regs[PORT_C].psor &= ~(0x00003000);
+ IMM->io_regs[PORT_C].pdir &= ~(0x00003000);
+
+ // Connect clk13 to RxClk and clk14 to TxClk on FCC2
+ IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks
+ IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks (see 15-14)
+ IMM->cpm_mux_cmxuar = 0x0000; // Utopia address reg, just clear
+
+ // Initialize parallel port registers to connect FCC2 to MII
+ IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31
+ IMM->io_regs[PORT_B].psor &= 0xffffc000;
+ IMM->io_regs[PORT_B].pdir &= 0xffffc000;
+
+ IMM->io_regs[PORT_B].psor |= 0x00000004;
+ IMM->io_regs[PORT_B].pdir |= 0x000003c5;
+ IMM->io_regs[PORT_B].ppar |= 0x00003fff;
+
+ // Initialize Receive Buffer Descriptors
+ qi->rbase = fec_eth_rxring;
+ qi->rxbd = fec_eth_rxring;
+ qi->rnext = fec_eth_rxring;
+ c_ptr = fec_eth_rxbufs;
+
+ for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) {
+
+ fec_eth_rxring[i].ctrl = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int);
+ fec_eth_rxring[i].length = 0; // reset
+ c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
+ fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr;
+ c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
+ }
+
+ fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap;
+
+ // Initialize Transmit Buffer Descriptors
+ qi->tbase = fec_eth_txring;
+ qi->txbd = fec_eth_txring;
+ qi->tnext = fec_eth_txring;
+ c_ptr = fec_eth_txbufs;
+
+ for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) {
+
+ fec_eth_txring[i].ctrl = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int);
+ fec_eth_txring[i].length = 0; // reset : Write before send
+ c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
+ fec_eth_txring[i].buffer = (volatile unsigned char *)c_ptr;
+ c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
+ }
+
+ fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap;
+
+ // Common FCC Parameter RAM initialization
+ fcc->riptr = FEC_PRAM_RIPTR; // in dual port RAM (see 28-11)
+ fcc->tiptr = FEC_PRAM_TIPTR; // in dual port RAM (see 28-11)
+ fcc->mrblr = FEC_PRAM_MRBLR; // ?? FROM 8101 code ...
+ fcc->rstate &= FEC_FCR_INIT;
+ fcc->rstate |= FEC_FCR_MOT_BO;
+ fcc->rbase = (long) fec_eth_rxring;
+ fcc->tstate &= FEC_FCR_INIT;
+ fcc->tstate |= FEC_FCR_MOT_BO;
+ fcc->tbase = (long) fec_eth_txring;
+
+ // Ethernet Specific FCC Parameter RAM Initialization
+ E_fcc->c_mask = FEC_PRAM_C_MASK; // (see 30-9)
+ E_fcc->c_pres = FEC_PRAM_C_PRES;
+ E_fcc->crcec = 0;
+ E_fcc->alec = 0;
+ E_fcc->disfc = 0;
+ E_fcc->ret_lim = FEC_PRAM_RETLIM;
+ E_fcc->p_per = FEC_PRAM_PER_LO;
+ E_fcc->gaddr_h = 0;
+ E_fcc->gaddr_l = 0;
+ E_fcc->tfcstat = 0;
+ E_fcc->mflr = FEC_MAX_FLR;
+
+ // Try to read the ethernet address of the transciever ...
+#ifdef CYGPKG_REDBOOT
+ esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
+#else
+ esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "fec_esa", enaddr, CONFIG_ESA);
+#endif
+ if (!esa_ok) {
+ // If can't use the default ...
+ os_printf("FEC_ETH - Warning! ESA unknown\n");
+ memcpy(enaddr, _default_enaddr, sizeof(enaddr));
+ }
+
+ E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2];
+ E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1];
+ E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0];
+
+ E_fcc->iaddr_h = 0;
+ E_fcc->iaddr_l = 0;
+ E_fcc->minflr = FEC_MIN_FLR;
+ E_fcc->taddr_h = 0;
+ E_fcc->taddr_m = 0;
+ E_fcc->taddr_l = 0;
+ E_fcc->pad_ptr = FEC_PRAM_TIPTR; // No special padding char ...
+ E_fcc->cf_type = 0;
+ E_fcc->maxd1 = FEC_PRAM_MAXD;
+ E_fcc->maxd2 = FEC_PRAM_MAXD;
+
+ // FCC register initialization
+ IMM->fcc_regs[FCC2].fcc_gfmr = FEC_GFMR_INIT;
+ IMM->fcc_regs[FCC2].fcc_psmr = FEC_PSMR_INIT;
+ IMM->fcc_regs[FCC2].fcc_dsr = FEC_DSR_INIT;
+
+#ifdef CYGPKG_NET
+ // clear the events of FCC2
+ IMM->fcc_regs[FCC2].fcc_fcce = 0xFFFF0000;
+ IMM->fcc_regs[FCC2].fcc_fccm = FEC_EV_TXE | FEC_EV_TXB | FEC_EV_RXF;
+
+ // Set up to handle interrupts
+ cyg_drv_interrupt_create(FEC_ETH_INT,
+ 0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
+ (cyg_addrword_t)sc, // Data passed to ISR
+ (cyg_ISR_t *)fec_eth_isr,
+ (cyg_DSR_t *)eth_drv_dsr,
+ &fec_eth_interrupt_handle,
+ &fec_eth_interrupt);
+ cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
+ cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
+ cyg_drv_interrupt_unmask(FEC_ETH_INT);
+#else
+
+ // Mask the interrupts
+ IMM->fcc_regs[FCC2].fcc_fccm = 0;
+#endif
+
+ // Issue Init RX & TX Parameters Command for FCC2
+ while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
+
+ IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
+ CPCR_FCC2_CH |
+ CPCR_MCN_FEC |
+ CPCR_FLG; /* ISSUE COMMAND */
+
+ while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
+
+ if (cache_state)
+ HAL_DCACHE_ENABLE();
+
+ // Initialize upper level driver for ecos
+ (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
+
+ return true;
+}
+
+//
+// This function is called to "start up" the interface. It may be called
+// multiple times, even when the hardware is already running. It will be
+// called whenever something "hardware oriented" changes and should leave
+// the hardware ready to send/receive packets.
+//
+static void
+fec_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+
+ // Enable the device :
+ // Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive
+ qi->fcc_reg->fcc_gfmr |= (FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
+
+}
+
+//
+// This function is called to shut down the interface.
+//
+static void
+fec_eth_stop(struct eth_drv_sc *sc)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+
+ // Disable the device :
+ // Clear the ENT/ENR bits in the GFMR -- Disable Transmit/Receive
+ qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
+}
+
+
+//
+// This function is called for low level "control" operations
+//
+static int
+fec_eth_control(struct eth_drv_sc *sc, unsigned long key,
+ void *data, int length)
+{
+ switch (key) {
+ case ETH_DRV_SET_MAC_ADDRESS:
+ return 0;
+ break;
+ default:
+ return 1;
+ break;
+ }
+}
+
+
+//
+// This function is called to see if another packet can be sent.
+// It should return the number of packets which can be handled.
+// Zero should be returned if the interface is busy and can not send any more.
+//
+static int
+fec_eth_can_send(struct eth_drv_sc *sc)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+ volatile struct fec_bd *txbd = qi->txbd;
+ int cache_state;
+
+ HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FEC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fec_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
+ }
+#endif
+
+ return ((txbd->ctrl & FEC_BD_Tx_Ready) == 0);
+}
+
+//
+// This routine is called to send data to the hardware.
+static void
+fec_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
+ int total_len, unsigned long key)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+ struct fec_bd *txbd, *txfirst;
+ volatile char *bp;
+ int i, txindex, cache_state;
+
+ HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FEC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fec_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
+ }
+#endif
+
+ // Find a free buffer
+ txbd = txfirst = qi->txbd;
+ while (txbd->ctrl & FEC_BD_Tx_Ready) {
+ // This buffer is busy, move to next one
+ if (txbd->ctrl & FEC_BD_Tx_Wrap) {
+ txbd = qi->tbase;
+ } else {
+ txbd++;
+ }
+ if (txbd == txfirst) {
+#ifdef CYGPKG_NET
+ panic ("No free xmit buffers");
+#else
+ os_printf("FEC Ethernet: No free xmit buffers\n");
+#endif
+ }
+ }
+
+ // Remember the next buffer to try
+ if (txbd->ctrl & FEC_BD_Tx_Wrap) {
+ qi->txbd = qi->tbase;
+ } else {
+ qi->txbd = txbd+1;
+ }
+
+ txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
+ qi->txkey[txindex] = key;
+
+ // Set up buffer
+ txbd->length = total_len;
+ bp = txbd->buffer;
+ for (i = 0; i < sg_len; i++) {
+ memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
+ bp += sg_list[i].len;
+ }
+
+ // Make sure no stale data buffer ...
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(txbd->buffer, txbd->length);
+ }
+ // Send it on it's way
+ txbd->ctrl |= FEC_BD_Tx_Ready | FEC_BD_Tx_Last | FEC_BD_Tx_TC;
+#ifndef FEC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(fec_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
+ }
+#endif
+
+}
+
+//
+// This function is called when a packet has been received. It's job is
+// to prepare to unload the packet from the hardware. Once the length of
+// the packet is known, the upper layer of the driver can be told. When
+// the upper layer is ready to unload the packet, the internal function
+// 'fec_eth_recv' will be called to actually fetch it from the hardware.
+//
+static void
+fec_eth_RxEvent(struct eth_drv_sc *sc)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+ struct fec_bd *rxbd;
+ int cache_state;
+
+ HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FEC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fec_eth_rxring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM);
+ }
+#endif
+
+ rxbd = qi->rnext;
+ while ((rxbd->ctrl & FEC_BD_Rx_Empty) == 0) {
+ qi->rxbd = rxbd; // Save for callback
+
+ // This is the right way of doing it, but dcbi has a bug ...
+ // if (cache_state) {
+ // HAL_DCACHE_INVALIDATE(rxbd->buffer, rxbd->length);
+ // }
+ (sc->funs->eth_drv->recv)(sc, rxbd->length);
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(rxbd->buffer, rxbd->length);
+ }
+
+ rxbd->ctrl |= FEC_BD_Rx_Empty;
+ if (rxbd->ctrl & FEC_BD_Rx_Wrap) {
+ rxbd = qi->rbase;
+ } else {
+ rxbd++;
+ }
+ }
+ // Remember where we left off
+ qi->rnext = (struct fec_bd *)rxbd;
+
+ // Make sure no stale data
+#ifndef FEC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(fec_eth_rxring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM);
+ }
+#endif
+
+}
+
+//
+// This function is called as a result of the "eth_drv_recv()" call above.
+// It's job is to actually fetch data for a packet from the hardware once
+// memory buffers have been allocated for the packet. Note that the buffers
+// may come in pieces, using a scatter-gather list. This allows for more
+// efficient processing in the upper layers of the stack.
+//
+static void
+fec_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+ unsigned char *bp;
+ int i;
+
+ bp = (unsigned char *)qi->rxbd->buffer;
+
+ for (i = 0; i < sg_len; i++) {
+ if (sg_list[i].buf != 0) {
+ memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
+ bp += sg_list[i].len;
+ }
+ }
+
+}
+
+static void
+fec_eth_TxEvent(struct eth_drv_sc *sc, int stat)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+ struct fec_bd *txbd;
+ int txindex, cache_state;
+
+ // Make sure no stale data
+ HAL_DCACHE_IS_ENABLED(cache_state);
+#ifndef FEC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_INVALIDATE(fec_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
+ }
+#endif
+
+ txbd = qi->tnext;
+ // Note: TC field is used to indicate the buffer has/had data in it
+ while ( (txbd->ctrl & (FEC_BD_Tx_TC | FEC_BD_Tx_Ready)) == FEC_BD_Tx_TC ) {
+ txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
+ (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
+ txbd->ctrl &= ~FEC_BD_Tx_TC;
+ if (txbd->ctrl & FEC_BD_Tx_Wrap) {
+ txbd = qi->tbase;
+ } else {
+ txbd++;
+ }
+ }
+ // Remember where we left off
+ qi->tnext = (struct fec_bd *)txbd;
+
+ // Make sure no stale data
+#ifndef FEC_BDs_NONCACHED
+ if (cache_state) {
+ HAL_DCACHE_FLUSH(fec_eth_txring,
+ 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
+ }
+#endif
+
+}
+
+//
+// Interrupt processing
+//
+static void
+fec_eth_int(struct eth_drv_sc *sc)
+{
+ struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
+ unsigned long iEvent;
+
+ while ((iEvent = qi->fcc_reg->fcc_fcce) != 0){
+
+ // Writing 1's clear fcce, Writing 0's have no effect
+ qi->fcc_reg->fcc_fcce = iEvent;
+
+ // Tx Done or Tx Error
+ if ( iEvent & (FEC_EV_TXB | FEC_EV_TXE) ) {
+ fec_eth_TxEvent(sc, iEvent);
+ }
+
+ // Complete or non-complete frame receive
+ if (iEvent & (FEC_EV_RXF | FEC_EV_RXB) ) {
+ fec_eth_RxEvent(sc);
+ }
+
+ }
+
+
+}
+
+//
+// Interrupt vector
+//
+static int
+fec_eth_int_vector(struct eth_drv_sc *sc)
+{
+ return (FEC_ETH_INT);
+}
+
Index: devs/eth/powerpc/quicc2/current/src/types.h
===================================================================
RCS file: devs/eth/powerpc/quicc2/current/src/types.h
diff -N devs/eth/powerpc/quicc2/current/src/types.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/quicc2/current/src/types.h 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,100 @@
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+/**********************************************************************
+ * Copyright (c) 1999 Delphi Communication Systems
+ * Maynard, MA. ALL RIGHTS RESERVED
+ ***********************************************************************/
+/**********************************************************************
+ * File:
+ * $RCSfile: types.h,v $
+ * $Revision: 1.1.1.2 $
+ * $Date: 2002/03/14 17:54:24 $
+ *
+ * Purpose:
+ * This file defines basic types used in the ITU-T G.729A Speech
+ * codec. These are defined here so that we may control
+ * how many bits of precision a type has on a particular
+ * platform.
+ *
+ * Operation:
+ * We define the following in this file:
+ *
+ * typedef ... INT16
+ * This type definition defines the data type used for
+ * variables that must hold exactly 16 bits (signed).
+ *
+ * typedef ... INT32
+ * This type definition defines the data type used for
+ * variables that must hold exactly 32 bits (signed).
+ *
+ * Notes/Issues:
+ * This file is correct for the following platforms (so far):
+ *
+ * GNUWIN32 compiled with GCC
+ *
+ * $Log: types.h,v $
+ * Revision 1.1.1.2 2002/03/14 17:54:24 pfine
+ * Fixed CR/LF Problem
+ *
+ * Revision 1.1.1.1 2002/03/13 18:20:24 pfine
+ * DCS Ecos with Device Drivers
+ *
+ *
+ ***********************************************************************/
+#ifndef TYPES_H
+#define TYPES_H
+
+typedef char INT8;
+typedef unsigned char UINT8;
+typedef short INT16;
+typedef unsigned short UINT16;
+typedef long INT32;
+typedef unsigned long UINT32;
+
+typedef volatile char VINT8;
+typedef volatile unsigned char VUINT8;
+typedef volatile short VINT16;
+typedef volatile unsigned short VUINT16;
+typedef volatile long VINT32;
+typedef volatile unsigned long VUINT32;
+
+typedef char OCTET;
+typedef int INT_NATIVE;
+typedef unsigned int UINT_NATIVE;
+
+#endif /* TYPES_H */
+
+
+
+
Index: devs/flash/intel/28fxxx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/intel/28fxxx/current/ChangeLog,v
retrieving revision 1.10
diff -u -5 -p -r1.10 ChangeLog
--- devs/flash/intel/28fxxx/current/ChangeLog 5 Aug 2002 13:31:36 -0000 1.10
+++ devs/flash/intel/28fxxx/current/ChangeLog 12 Dec 2002 20:55:01 -0000
@@ -1,5 +1,12 @@
+2002-12-12 Gary Thomas <gthomas@ecoscentric.com>
+2002-12-12 Patrick Doyle <wpd@delcomsys.com>
+
+ * include/flash_28fxxx_parts.inl:
+ * include/flash_28fxxx.inl:
+ * cdl/flash_intel_28fxxx.cdl: Add SHARP 28F016 parts.
+
2002-08-05 Gary Thomas <gary@chez-thomas.org>
2002-08-05 Jani Monoses <jani@iv.ro>
* include/flash_28fxxx_parts.inl:
* cdl/flash_intel_28fxxx.cdl: Add support for 28F320B3.
Index: devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl,v
retrieving revision 1.6
diff -u -5 -p -r1.6 flash_intel_28fxxx.cdl
--- devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl 5 Aug 2002 13:31:36 -0000 1.6
+++ devs/flash/intel/28fxxx/current/cdl/flash_intel_28fxxx.cdl 12 Dec 2002 20:31:23 -0000
@@ -113,6 +113,32 @@ cdl_package CYGPKG_DEVS_FLASH_INTEL_28FX
description "
When this option is enabled, the Intel flash driver will be
able to recognize and handle the 28F320S3
part in the family."
}
+
+ cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 {
+ display "Sharp LH28F016SCT-Z4 flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the Sharp LH28F016SCT-Z4
+ part. Although this part is not an Intel part, the driver
+ is implemented using the same command status definitions."
+
+ }
+
+ cdl_option CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 {
+ display "Sharp LH28F016SCT-95 flash memory support"
+ default_value 0
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+ implements CYGINT_DEVS_FLASH_INTEL_VARIANTS
+ description "
+ When this option is enabled, the Intel flash driver will be
+ able to recognize and handle the Sharp LH28F016SCT-95
+ part. Although this part is not an Intel part, the driver
+ is implemented using the same command status definitions."
+
+ }
}
Index: devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl,v
retrieving revision 1.7
diff -u -5 -p -r1.7 flash_28fxxx.inl
--- devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl 23 May 2002 23:01:01 -0000 1.7
+++ devs/flash/intel/28fxxx/current/include/flash_28fxxx.inl 12 Dec 2002 20:53:46 -0000
@@ -9,10 +9,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -531,10 +532,112 @@ flash_unlock_block(void* block, int bloc
int res = FLASH_ERR_OK;
flash_data_t state;
int timeout = 5000000;
volatile flash_data_t* b_p = (flash_data_t*) block;
volatile flash_data_t *b_v;
+
+#if (defined(CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4) || defined(CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95) )
+ // The Sharp device follows all the same rules as the Intel 28x part,
+ // except that the unlocking mechanism unlocks all blocks at once. This
+ // is the way the Strata part seems to work. I will replace the
+ // flash_unlock_block function with one similar to the Strata function.
+ // As the Sharp part does not have the bootlock characteristics, I
+ // will ignore them.
+//
+// The difficulty with this operation is that the hardware does not support
+// unlocking single blocks. However, the logical layer would like this to
+// be the case, so this routine emulates it. The hardware can clear all of
+// the locks in the device at once. This routine will use that approach and
+// then reset the regions which are known to be locked.
+//
+
+#define MAX_FLASH_BLOCKS (flash_dev_info->block_count * CYGNUM_FLASH_SERIES)
+
+ unsigned char is_locked[MAX_FLASH_BLOCKS];
+ int i;
+
+ // Get base address and map addresses to virtual addresses
+#ifdef DEBUG
+ d_print("\nNow inside low level driver\n");
+#endif
+ ROM = (volatile flash_data_t*) CYGNUM_FLASH_BASE;
+ block = FLASH_P2V(block);
+
+ // Clear any error conditions
+ ROM[0] = FLASH_Clear_Status;
+
+ // Get current block lock state. This needs to access each block on
+ // the device so currently locked blocks can be re-locked.
+ b_p = ROM;
+ for (i = 0; i < blocks; i++) {
+ b_v = FLASH_P2V( b_p );
+ *b_v = FLASH_Read_ID;
+ if (b_v == block) {
+ is_locked[i] = 0;
+ } else {
+ if(b_v[2]){ /* it is possible that one of the interleaved devices
+ * is locked, but others are not. Coming out of this
+ * function, if one was locked, all will be locked.
+ */
+ is_locked[i] = 1;
+ }else{
+ is_locked[i] = 0;
+ }
+ }
+#ifdef DEBUG
+#endif
+ b_p += block_size / sizeof(*b_p);
+ }
+ ROM[0] = FLASH_Reset;
+#ifdef DEBUG
+ for (i = 0; i < blocks; i++) {
+ d_print("\nblock %d %s", i,
+ is_locked[i] ? "LOCKED" : "UNLOCKED");
+ }
+ d_print("\n");
+#endif
+
+ // Clears all lock bits
+ ROM[0] = FLASH_Clear_Lock;
+ ROM[0] = FLASH_Clear_Lock_Confirm; // Confirmation
+ timeout = 5000000;
+ while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
+ if (--timeout == 0) break;
+ }
+
+ // Restore the lock state
+ b_p = ROM;
+ for (i = 0; i < blocks; i++) {
+ b_v = FLASH_P2V( b_p );
+ if (is_locked[i]) {
+ *b_v = FLASH_Set_Lock;
+ *b_v = FLASH_Set_Lock_Confirm; // Confirmation
+ timeout = 5000000;
+ while(((state = ROM[0]) & FLASH_Status_Ready)
+ != FLASH_Status_Ready) {
+ if (--timeout == 0){
+ res = FLASH_ERR_DRV_TIMEOUT;
+ break;
+ }
+ }
+ if (FLASH_ErrorLock == (state & FLASH_ErrorLock))
+ res = FLASH_ERR_LOCK;
+
+ if (res != FLASH_ERR_OK)
+ break;
+
+ }
+ b_p += block_size / sizeof(*b_p);
+ }
+
+ // Restore ROM to "normal" mode
+ ROM[0] = FLASH_Reset;
+
+ return res;
+
+#else // not CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4
+
cyg_bool bootblock;
int len, len_ix = 1;
if (!flash_dev_info->locking)
return res;
@@ -654,9 +757,10 @@ flash_unlock_block(void* block, int bloc
}
// Restore ROM to "normal" mode
ROM[0] = FLASH_Reset;
#endif
+#endif // #CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4
}
#endif // CYGHWR_IO_FLASH_BLOCK_LOCKING
#endif // CYGONCE_DEVS_FLASH_INTEL_28FXXX_INL
Index: devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl,v
retrieving revision 1.6
diff -u -5 -p -r1.6 flash_28fxxx_parts.inl
--- devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl 5 Aug 2002 13:31:36 -0000 1.6
+++ devs/flash/intel/28fxxx/current/include/flash_28fxxx_parts.inl 12 Dec 2002 20:31:23 -0000
@@ -54,10 +54,37 @@
//####DESCRIPTIONEND####
//
//==========================================================================
#if CYGNUM_FLASH_WIDTH == 8
+#ifdef CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4
+ { // LH28F016SCT_Z4
+ device_id : FLASHWORD(0xA0),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 32,
+ device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ buffered_w : false,
+ locking : true,
+ bootblock : false,
+ banked : false
+ },
+#endif
+
+#ifdef CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95
+ { // LH28F016SCT_95
+ device_id : FLASHWORD(0xAA),
+ block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 32,
+ device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ buffered_w : false,
+ locking : true,
+ bootblock : false,
+ banked : false
+ },
+#endif
#else // 16 bit devices
#ifdef CYGHWR_DEVS_FLASH_INTEL_28F320C3
{ // 28F320C3-T
Index: devs/flash/powerpc/ts6/current/ChangeLog
===================================================================
RCS file: devs/flash/powerpc/ts6/current/ChangeLog
diff -N devs/flash/powerpc/ts6/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/ts6/current/ChangeLog 12 Dec 2002 20:55:09 -0000
@@ -0,0 +1,42 @@
+2002-12-12 Gary Thomas <gthomas@ecoscentric.com>
+2002-12-12 Patrick Doyle <wpd@delcomsys.com>
+
+ * src/powerpc_ts6_flash.c:
+ * cdl/flash_ts6.cdl: New package - FLASH support on Delphi
+ Communications TS6 board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/flash/powerpc/ts6/current/cdl/flash_ts6.cdl
===================================================================
RCS file: devs/flash/powerpc/ts6/current/cdl/flash_ts6.cdl
diff -N devs/flash/powerpc/ts6/current/cdl/flash_ts6.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/ts6/current/cdl/flash_ts6.cdl 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,72 @@
+# ====================================================================
+#
+# flash_ts6.cdl
+#
+# FLASH memory - Hardware support on Delphi MPC8260 TS6 Board
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): pfine
+# Original data: gthomas
+# Contributors:
+# Date: 2002-02-27
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_TS6 {
+ display "Delphi TS6 FLASH memory support"
+
+ parent CYGPKG_IO_FLASH
+ active_if CYGPKG_IO_FLASH
+ requires CYGPKG_HAL_POWERPC_TS6
+
+ implements CYGHWR_IO_FLASH_DEVICE
+
+ compile powerpc_ts6_flash.c
+
+ # Arguably this should do in the generic package
+ # but then there is a logic loop so you can never enable it.
+ cdl_interface CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED {
+ display "Generic INTEL 28FXXX driver required"
+ }
+
+ implements CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED
+ requires (CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95 || CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4)
+}
Index: devs/flash/powerpc/ts6/current/src/powerpc_ts6_flash.c
===================================================================
RCS file: devs/flash/powerpc/ts6/current/src/powerpc_ts6_flash.c
diff -N devs/flash/powerpc/ts6/current/src/powerpc_ts6_flash.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/ts6/current/src/powerpc_ts6_flash.c 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,71 @@
+//==========================================================================
+//
+// powerpc_ts6_flash.c
+//
+// Flash programming for SHARP device on DELPHI TS6 board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): pfine
+// Original: jskov
+// Contributors:
+// Date: 2002-02-27
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+//--------------------------------------------------------------------------
+// Device properties
+
+#define CYGNUM_FLASH_INTERLEAVE (4)
+#define CYGNUM_FLASH_SERIES (1)
+#define CYGNUM_FLASH_WIDTH (8)
+#define CYGNUM_FLASH_BASE (0xff800000u)
+
+//--------------------------------------------------------------------------
+// Platform specific extras
+
+//--------------------------------------------------------------------------
+// Now include the driver code.
+#include "cyg/io/flash_28fxxx.inl"
+
+// ------------------------------------------------------------------------
+// EOF powerpc_ts6_flash.c
Index: devs/flash/powerpc/vads/current/ChangeLog
===================================================================
RCS file: devs/flash/powerpc/vads/current/ChangeLog
diff -N devs/flash/powerpc/vads/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/vads/current/ChangeLog 12 Dec 2002 20:55:44 -0000
@@ -0,0 +1,42 @@
+2002-12-12 Gary Thomas <gthomas@ecoscentric.com>
+2002-12-12 Patrick Doyle <wpd@delcomsys.com>
+
+ * src/powerpc_vads_flash.c:
+ * cdl/flash_vads.cdl: New package - FLASH support on Motorola
+ VADS (MPC8260) system.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/flash/powerpc/vads/current/cdl/flash_vads.cdl
===================================================================
RCS file: devs/flash/powerpc/vads/current/cdl/flash_vads.cdl
diff -N devs/flash/powerpc/vads/current/cdl/flash_vads.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/vads/current/cdl/flash_vads.cdl 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,73 @@
+# ====================================================================
+#
+# flash_vads.cdl
+#
+# FLASH memory - Hardware support on Motorola MPC8260 Voyager Board
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): pfine
+# Original data: gthomas
+# Contributors:
+# Date: 2002-01-11
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_VADS {
+ display "Motorola MPC8260 Voyager ADS FLASH memory support"
+
+ parent CYGPKG_IO_FLASH
+ active_if CYGPKG_IO_FLASH
+ requires CYGPKG_HAL_POWERPC_VADS
+
+ implements CYGHWR_IO_FLASH_DEVICE
+# implements CYGHWR_IO_FLASH_DEVICE_NOT_IN_RAM
+
+ compile powerpc_vads_flash.c
+
+ # Arguably this should do in the generic package
+ # but then there is a logic loop so you can never enable it.
+ cdl_interface CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED {
+ display "Generic INTEL 28FXXX driver required"
+ }
+
+ implements CYGINT_DEVS_FLASH_INTEL_28FXXX_REQUIRED
+ requires (CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4 || CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95)
+}
Index: devs/flash/powerpc/vads/current/src/powerpc_vads_flash.c
===================================================================
RCS file: devs/flash/powerpc/vads/current/src/powerpc_vads_flash.c
diff -N devs/flash/powerpc/vads/current/src/powerpc_vads_flash.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/vads/current/src/powerpc_vads_flash.c 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,77 @@
+//==========================================================================
+//
+// powerpc_vads_flash.c
+//
+// Flash programming for SHARP device on POWERPC MPC8260 Voyager
+// ADS board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): pfine
+// Original: jskov
+// Contributors:
+// Date: 2002-01-11
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+//--------------------------------------------------------------------------
+// Device properties
+
+#define CYGNUM_FLASH_INTERLEAVE (4)
+#define CYGNUM_FLASH_SERIES (1)
+#define CYGNUM_FLASH_WIDTH (8)
+#define nPF_HACK
+#ifdef PF_HACK
+#define CYGNUM_FLASH_BASE (0xfe000000u)
+#else
+#define CYGNUM_FLASH_BASE (0xff800000u)
+#endif
+
+//--------------------------------------------------------------------------
+// Platform specific extras
+
+//--------------------------------------------------------------------------
+// Now include the driver code.
+#include "cyg/io/flash_28fxxx.inl"
+
+// ------------------------------------------------------------------------
+// EOF powerpc_vads_flash.c
Index: devs/serial/powerpc/quicc2/current/ChangeLog
===================================================================
RCS file: devs/serial/powerpc/quicc2/current/ChangeLog
diff -N devs/serial/powerpc/quicc2/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/serial/powerpc/quicc2/current/ChangeLog 12 Dec 2002 20:56:25 -0000
@@ -0,0 +1,43 @@
+2002-12-12 Gary Thomas <gthomas@ecoscentric.com>
+2002-12-12 Patrick Doyle <wpd@delcomsys.com>
+
+ * src/quicc2_scc_serial.h:
+ * src/quicc2_scc_serial.c:
+ * cdl/ser_quicc2_scc.cdl: New package - serial I/O suport on
+ PowerPC/QUICC2 based systems (like MPC8260).
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl
===================================================================
RCS file: devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl
diff -N devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/serial/powerpc/quicc2/current/cdl/ser_quicc2_scc.cdl 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,290 @@
+# ====================================================================
+#
+# ser_quicc2_scc.cdl
+#
+# eCos serial PowerPC/QUICC2 SCC configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): mtek
+# Original data: gthomas
+# Contributors:
+# Date: 2002-02-27
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+
+cdl_package CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC {
+ display "PowerPC QUICC2/SCC serial device drivers"
+
+ parent CYGPKG_IO_SERIAL_DEVICES
+ active_if CYGPKG_IO_SERIAL
+ active_if CYGPKG_HAL_POWERPC_MPC8260
+
+ requires CYGPKG_ERROR
+ include_dir cyg/io
+ include_files ; # none _exported_ whatsoever
+ description "
+ This option enables the serial device drivers for the
+ PowerPC QUICC2/SCC."
+ doc redirect/ecos-device-drivers.html
+
+ compile -library=libextras.a quicc2_scc_serial.c
+
+ define_proc {
+ puts $::cdl_system_header "/***** serial driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_powerpc_quicc2_scc.h>"
+ puts $::cdl_system_header "/***** serial driver proc output end *****/"
+ }
+
+cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1 {
+ display "PowerPC QUICC2/SCC serial port 1 driver"
+ flavor bool
+ default_value 1
+ description "
+ This option includes the serial device driver for the PowerPC
+ QUICC2/SCC port 1."
+
+ cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_NAME {
+ display "Device name for PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ default_value {"\"/dev/ser1\""}
+ description "
+ This option specifies the device name for the PowerPC
+ QUICC2/SCC port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD {
+ display "Baud rate for the PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+ 4800 7200 9600 14400 19200 38400 57600 115200 230400
+ }
+ default_value 9600
+ description "
+ This option specifies the default baud rate (speed) for the
+ PowerPC QUICC2/SCC port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE {
+ display "Buffer size for the PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ legal_values 0 to 8192
+ default_value 256
+ description "
+ This option specifies the size of the internal buffers used
+ for the PowerPC QUICC2/SCC port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BRG {
+ display "Which baud rate generator to use for the PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ legal_values 1 to 4
+ default_value 1
+ description "
+ This option specifies which of the four baud rate generators
+ to use for the PowerPC QUICC2/SCC port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE {
+ display "Output buffer size for the PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ legal_values 16 to 128
+ default_value 16
+ description "
+ This option specifies the maximum number of characters per
+ transmit request to be used for the PowerPC QUICC2/SCC port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM {
+ display "Number of output buffers for the PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ legal_values 2 to 16
+ default_value 4
+ description "
+ This option specifies the number of output buffer packets
+ to be used for the PowerPC QUICC2/SCC port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE {
+ display "Input buffer size for the PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ legal_values 16 to 128
+ default_value 16
+ description "
+ This option specifies the maximum number of characters per receive
+ request to be used for the PowerPC QUICC2/SCC port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM {
+ display "Number of input buffers for the PowerPC QUICC2/SCC serial port 1"
+ flavor data
+ legal_values 2 to 16
+ default_value 4
+ description "
+ This option specifies the number of input buffer packets
+ to be used for the PowerPC QUICC2/SCC port 1."
+ }
+}
+
+cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2 {
+ display "PowerPC QUICC2/SCC serial port 2 driver"
+ flavor bool
+ default_value 1
+ description "
+ This option includes the serial device driver for the PowerPC
+ QUICC2/SCC port 2."
+
+ cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_NAME {
+ display "Device name for PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ default_value {"\"/dev/ser2\""}
+ description "
+ This option specifies the device name for the PowerPC
+ QUICC2/SCC port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD {
+ display "Baud rate for the PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+ 4800 7200 9600 14400 19200 38400 57600 115200 230400
+ }
+ default_value 9600
+ description "
+ This option specifies the default baud rate (speed) for the
+ PowerPC QUICC2/SCC port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE {
+ display "Buffer size for the PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ legal_values 0 to 8192
+ default_value 256
+ description "
+ This option specifies the size of the internal buffers used
+ for the PowerPC QUICC2/SCC port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BRG {
+ display "Which baud rate generator to use for the PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ legal_values 1 to 4
+ default_value 2
+ description "
+ This option specifies which of the four baud rate generators
+ to use for the PowerPC QUICC2/SCC port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE {
+ display "Output buffer size for the PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ legal_values 16 to 128
+ default_value 16
+ description "
+ This option specifies the maximum number of characters per
+ transmit request to be used for the PowerPC QUICC2/SCC port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM {
+ display "Number of output buffers for the PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ legal_values 2 to 16
+ default_value 4
+ description "
+ This option specifies the number of output buffer packets
+ to be used for the PowerPC QUICC2/SCC port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE {
+ display "Input buffer size for the PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ legal_values 16 to 128
+ default_value 16
+ description "
+ This option specifies the maximum number of characters per receive
+ request to be used for the PowerPC QUICC2/SCC port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM {
+ display "Number of output buffers for the PowerPC QUICC2/SCC serial port 2"
+ flavor data
+ legal_values 2 to 16
+ default_value 4
+ description "
+ This option specifies the number of input buffer packets
+ to be used for the PowerPC QUICC2/SCC port 2."
+ }
+}
+
+ cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_OPTIONS {
+ display "Serial device driver build options"
+ flavor none
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+
+ cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building these serial device drivers. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building these serial device drivers. These flags are removed from
+ the set of global flags if present."
+ }
+ }
+}
+
+# EOF ser_quicc_smc.cdl
Index: devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c
===================================================================
RCS file: devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c
diff -N devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/serial/powerpc/quicc2/current/src/quicc2_scc_serial.c 12 Dec 2002 20:31:23 -0000
@@ -0,0 +1,851 @@
+//==========================================================================
+//
+// io/serial/powerpc/quicc2_scc_serial.c
+//
+// PowerPC QUICC2 (SCC) Serial I/O Interface Module (interrupt driven)
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): mtek
+// Contributors: gthomas
+// Date: 1999-06-20
+// Purpose: QUICC2 SCC Serial I/O module (interrupt driven version)
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/io_serial.h>
+#include <pkgconf/io.h>
+#include <cyg/io/io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/var_intr.h>
+#include <cyg/io/devtab.h>
+#include <cyg/io/serial.h>
+#include <cyg/infra/diag.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/mpc8260.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include "quicc2_scc_serial.h"
+#define QUICC2_VADS_IMM_BASE 0x04700000
+#define QUICC2_VADS_BCSR_BASE 0x04500000
+
+#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
+
+static bool
+quicc2_scc_serial_init(struct cyg_devtab_entry *tab);
+static bool
+quicc2_scc_serial_putc(serial_channel *chan,
+ unsigned char c);
+static Cyg_ErrNo
+quicc2_scc_serial_lookup(struct cyg_devtab_entry **tab,
+ struct cyg_devtab_entry *sub_tab,
+ const char *name);
+static unsigned char
+quicc2_scc_serial_getc(serial_channel *chan);
+static Cyg_ErrNo
+quicc2_scc_serial_set_config(serial_channel *chan,
+ cyg_uint32 key, const void *xbuf,
+ cyg_uint32 *len);
+static void
+quicc2_scc_serial_start_xmit(serial_channel *chan);
+static void
+quicc2_scc_serial_stop_xmit(serial_channel *chan);
+
+static cyg_uint32
+quicc2_scc_serial_ISR(cyg_vector_t vector,
+ cyg_addrword_t data);
+static void
+quicc2_scc_serial_DSR(cyg_vector_t vector,
+ cyg_ucount32 count,
+ cyg_addrword_t data);
+
+static SERIAL_FUNS(quicc2_scc_serial_funs,
+ quicc2_scc_serial_putc,
+ quicc2_scc_serial_getc,
+ quicc2_scc_serial_set_config,
+ quicc2_scc_serial_start_xmit,
+ quicc2_scc_serial_stop_xmit
+ );
+
+#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1
+static quicc2_scc_serial_info quicc2_scc_serial_info1;
+
+#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE > 0
+static unsigned char quicc2_scc_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE];
+static unsigned char quicc2_scc_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel1,
+ quicc2_scc_serial_funs,
+ quicc2_scc_serial_info1,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &quicc2_scc_serial_out_buf1[0], sizeof(quicc2_scc_serial_out_buf1),
+ &quicc2_scc_serial_in_buf1[0], sizeof(quicc2_scc_serial_in_buf1)
+ );
+#else
+static SERIAL_CHANNEL(quicc2_scc_serial_channel1,
+ quicc2_scc_serial_funs,
+ quicc2_scc_serial_info1,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+
+static unsigned char quicc2_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM]
+ [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
+static unsigned char quicc2_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM]
+ [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE + HAL_DCACHE_LINE_SIZE-1];
+
+DEVTAB_ENTRY(quicc2_scc_serial_io1,
+ CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_NAME,
+ 0, // Does not depend on a lower level interface
+ &cyg_io_serial_devio,
+ quicc2_scc_serial_init,
+ quicc2_scc_serial_lookup, // Serial driver may need initializing
+ &quicc2_scc_serial_channel1
+ );
+#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1
+
+#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2
+static quicc2_scc_serial_info quicc2_scc_serial_info2;
+
+#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE > 0
+static unsigned char quicc2_scc_serial_out_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE];
+static unsigned char quicc2_scc_serial_in_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel2,
+ quicc2_scc_serial_funs,
+ quicc2_scc_serial_info2,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &quicc2_scc_serial_out_buf2[0], sizeof(quicc2_scc_serial_out_buf2),
+ &quicc2_scc_serial_in_buf2[0], sizeof(quicc2_scc_serial_in_buf2)
+ );
+#else
+static SERIAL_CHANNEL(quicc2_scc_serial_channel2,
+ quicc2_scc_serial_funs,
+ quicc2_scc_serial_info2,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+static unsigned char quicc2_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM]
+ [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
+static unsigned char quicc2_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM]
+ [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE + HAL_DCACHE_LINE_SIZE-1];
+
+DEVTAB_ENTRY(quicc2_scc_serial_io2,
+ CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_NAME,
+ 0, // Does not depend on a lower level interface
+ &cyg_io_serial_devio,
+ quicc2_scc_serial_init,
+ quicc2_scc_serial_lookup, // Serial driver may need initializing
+ &quicc2_scc_serial_channel2
+ );
+#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC
+
+#ifdef CYGDBG_DIAG_BUF
+extern int enable_diag_uart;
+#endif // CYGDBG_DIAG_BUF
+
+// Internal function to actually configure the hardware to
+// desired baud rate, stop bits and parity ...
+static bool
+quicc2_scc_serial_config_port(serial_channel *chan,
+ cyg_serial_info_t *new_config,
+ bool init)
+{
+ quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv;
+ volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
+
+ unsigned long b_rate = select_baud[new_config->baud];
+
+ if (b_rate == 0) return false;
+
+ // Stop the transmitter while changing baud rate
+ while (IMM->cpm_cpcr & QUICC2_CPCR_READY);
+ IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_STOP_TX | QUICC2_CPCR_READY;
+ while (IMM->cpm_cpcr & QUICC2_CPCR_READY);
+
+ // Disable Tx, RX and put them in a reset state
+ scc_chan->scc_regs->gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR);
+
+ // Set the baud rate
+ *(scc_chan->brg) = (UART_BIT_RATE(b_rate) << 1) | QUICC2_BRG_EN;
+
+ // Set stop bits, word length and parity
+ scc_chan->scc_regs->psmr = QUICC2_SCC_PSMR_ASYNC |
+ select_stop_bits[new_config->stop] |
+ select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
+ select_parity[new_config->parity];
+
+ // Support fractional stop bits
+ scc_chan->scc_regs->dsr = (new_config->stop & 1) ? QUICC2_SCC_DSR_FULL : QUICC2_SCC_DSR_HALF;
+
+ // Initialize the parameters
+ while (IMM->cpm_cpcr & QUICC2_CPCR_READY);
+ IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_INIT_TX_RX | QUICC2_CPCR_READY;
+ while (IMM->cpm_cpcr & QUICC2_CPCR_READY);
+
+ // Enable Tx and Rx
+ scc_chan->scc_regs->gsmr_l |= (QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR);
+
+ if (new_config != &chan->config) {
+ chan->config = *new_config;
+ }
+ return true;
+}
+
+// Function to set up internal tables for device.
+static void
+quicc2_scc_serial_init_info(quicc2_scc_serial_info *scc_chan,
+ int SCC_index,
+ int BRG_index,
+ int TxBD, int TxNUM, int TxSIZE,
+ cyg_uint8 *TxBUF,
+ int RxBD, int RxNUM, int RxSIZE,
+ cyg_uint8 *RxBUF)
+{
+ volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
+#ifdef CYGPKG_HAL_POWERPC_VADS
+ volatile t_BCSR *bcsr = (volatile t_BCSR *) QUICC2_VADS_BCSR_BASE;
+#endif
+ t_UartScc_Pram *uart_pram;
+ scc_bd *txbd, *rxbd;
+ int i;
+
+ // Disable the channel, just in case
+ IMM->scc_regs[SCC_index-1].gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR);
+
+ switch (SCC_index) {
+
+ case 1:
+ // Put the data into the info structure
+ scc_chan->scc_cpcr = QUICC2_CPCR_SCC1;
+ scc_chan->scc_regs = &(IMM->scc_regs[0]);
+ scc_chan->scc_pram = &(IMM->pram.serials.scc_pram[0]);
+ scc_chan->int_vector = CYGNUM_HAL_INTERRUPT_SCC1;
+
+ // Set-up the PORT D pins
+ IMM->io_regs[PORT_D].psor &= ~QUICC2_SCC1_PORTD_PPAR;
+ IMM->io_regs[PORT_D].psor |= QUICC2_SCC1_PORTD_PDIR;
+ IMM->io_regs[PORT_D].ppar |= QUICC2_SCC1_PORTD_PPAR;
+ IMM->io_regs[PORT_D].pdir &= ~QUICC2_SCC1_PORTD_PPAR;
+ IMM->io_regs[PORT_D].pdir |= QUICC2_SCC1_PORTD_PDIR;
+ IMM->io_regs[PORT_D].podr &= ~QUICC2_SCC1_PORTD_PPAR;
+
+ // Set-up the PORT C pins
+ IMM->io_regs[PORT_C].psor &= ~QUICC2_SCC1_PORTC_PPAR;
+ IMM->io_regs[PORT_C].ppar |= QUICC2_SCC1_PORTC_PPAR;
+ IMM->io_regs[PORT_C].pdir &= ~QUICC2_SCC1_PORTC_PPAR;
+ IMM->io_regs[PORT_C].podr &= ~QUICC2_SCC1_PORTC_PPAR;
+
+ // Select the baud rate generator and connect it
+ IMM->cpm_mux_cmxscr &= QUICC2_CMX_SCC1_CLR;
+
+ switch (BRG_index) {
+ case 1:
+ scc_chan->brg = &(IMM->brgs_brgc1);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG1;
+ break;
+ case 2:
+ scc_chan->brg = &(IMM->brgs_brgc2);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG2;
+ break;
+ case 3:
+ scc_chan->brg = &(IMM->brgs_brgc3);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG3;
+ break;
+ case 4:
+ scc_chan->brg = &(IMM->brgs_brgc4);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC1_BRG4;
+ break;
+ }
+#ifdef CYGPKG_HAL_POWERPC_VADS
+ // Enable the transciever
+ bcsr->bcsr1 &= ~(QUICC2_BCSR_EN_SCC1);
+#endif
+ break;
+
+ case 2:
+ // Put the data into the info structure
+ scc_chan->scc_cpcr = QUICC2_CPCR_SCC2;
+ scc_chan->scc_regs = &(IMM->scc_regs[1]);
+ scc_chan->scc_pram = &(IMM->pram.serials.scc_pram[1]);
+ scc_chan->int_vector = CYGNUM_HAL_INTERRUPT_SCC2;
+
+ // Set-up the PORT D pins
+ IMM->io_regs[PORT_D].psor &= ~QUICC2_SCC2_PORTD_PPAR;
+ IMM->io_regs[PORT_D].ppar |= QUICC2_SCC2_PORTD_PPAR;
+ IMM->io_regs[PORT_D].pdir &= ~QUICC2_SCC2_PORTD_PPAR;
+ IMM->io_regs[PORT_D].pdir |= QUICC2_SCC2_PORTD_PDIR;
+ IMM->io_regs[PORT_D].podr &= ~QUICC2_SCC2_PORTD_PPAR;
+
+ // Set-up the PORT C pins
+ IMM->io_regs[PORT_C].psor &= ~QUICC2_SCC2_PORTC_PPAR;
+ IMM->io_regs[PORT_C].ppar |= QUICC2_SCC2_PORTC_PPAR;
+ IMM->io_regs[PORT_C].pdir &= ~QUICC2_SCC2_PORTC_PPAR;
+ IMM->io_regs[PORT_C].podr &= ~QUICC2_SCC2_PORTC_PPAR;
+
+ // Select the baud rate generator and connect it
+ IMM->cpm_mux_cmxscr &= QUICC2_CMX_SCC2_CLR;
+
+ switch (BRG_index) {
+ case 1:
+ scc_chan->brg = &(IMM->brgs_brgc1);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG1;
+ break;
+ case 2:
+ scc_chan->brg = &(IMM->brgs_brgc2);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG2;
+ break;
+ case 3:
+ scc_chan->brg = &(IMM->brgs_brgc3);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG3;
+ break;
+ case 4:
+ scc_chan->brg = &(IMM->brgs_brgc4);
+ IMM->cpm_mux_cmxscr |= QUICC2_CMX_SCC2_BRG4;
+ break;
+ }
+#ifdef CYGPKG_HAL_POWERPC_VADS
+ // Enable the transciever
+ bcsr->bcsr1 &= ~(QUICC2_BCSR_EN_SCC2);
+#endif
+ break;
+
+ default:
+ diag_printf("Incorrect SCC index in quicc2_scc_serial_init_info \n");
+ break;
+ }
+
+ // Initialize common SCC PRAM
+ scc_chan->tbase = (scc_bd *) (QUICC2_VADS_IMM_BASE + TxBD);
+ scc_chan->rbase = (scc_bd *) (QUICC2_VADS_IMM_BASE + RxBD);
+ scc_chan->txbd = (scc_bd *) (QUICC2_VADS_IMM_BASE + TxBD);
+ scc_chan->rxbd = (scc_bd *) (QUICC2_VADS_IMM_BASE + RxBD);
+ scc_chan->txsize = TxSIZE;
+ scc_chan->rxsize = RxSIZE;
+
+ scc_chan->scc_pram->rbase = RxBD;
+ scc_chan->scc_pram->tbase = TxBD;
+ scc_chan->scc_pram->rfcr = 0x10;
+ scc_chan->scc_pram->tfcr = 0x10;
+ scc_chan->scc_pram->mrblr = RxSIZE;
+
+ // Initialize UART PRAM
+ uart_pram = &(scc_chan->scc_pram->SpecificProtocol.u);
+
+ uart_pram->max_idl = 4;
+ uart_pram->brkcr = 1;
+ uart_pram->brkln = 0;
+ uart_pram->parec = 0;
+ uart_pram->frmec = 0;
+ uart_pram->nosec = 0;
+ uart_pram->brkec = 0;
+ uart_pram->uaddr1 = 0;
+ uart_pram->uaddr2 = 0;
+ uart_pram->toseq = 0;
+ uart_pram->cc[0] = 0x8000;
+ uart_pram->cc[1] = 0x8000;
+ uart_pram->cc[2] = 0x8000;
+ uart_pram->cc[3] = 0x8000;
+ uart_pram->cc[4] = 0x8000;
+ uart_pram->cc[5] = 0x8000;
+ uart_pram->cc[6] = 0x8000;
+ uart_pram->cc[7] = 0x8000;
+ uart_pram->rccm = 0xC0FF;
+
+ // Initialize registers
+ scc_chan->scc_regs->gsmr_l = QUICC2_SCC_GSMR_L_INIT;
+ scc_chan->scc_regs->gsmr_h = QUICC2_SCC_GSMR_H_INIT;
+ // scc_chan->scc_regs->psmr = 0x8000; // Set by config
+ scc_chan->scc_regs->todr = 0;
+ // scc_chan->scc_regs