RE: gcc compile

[Jens-Christian Lache <lache at tu-harburg dot de>]

Am Mon, 22 Jan 2001 schrieben Sie:
> > Unfortunately the ARM simulator does not support the several 
> > CPU modes, that
> > the ARM7TDMI has. I made a software trap using "swi", and the 
> > pc was set
> > correctly to 0x8. It did also execute the jump instruction 
> > from this place
> > leading to my own swi handler. But when leaving it, returning to the
> > code containing the swi, the mode was still 0x10, which is 
> > not supervisor
> > mode. 
> 
> 
> How do you return from your SWI handler? Don't forget
> you have to make
> 	movs	pc, lr
> to copy SPSR in CPSR at the same time you return, so
> the mode gets changed.
> 
> CPU modes have been in existence since the very beginning
> of the ARM cores, so I doubt it's not supported!
> 
> Cheers,
> Yves
Hello!
This is how the swi_handler looks like. You may have a look at the source code.
Please say make and run it on the gdb sim. In my opinion it wasn´t in SV.
I have tested the code on the eb01. After swi the proc is in SV.


Thank you all for your help!!!

Jens-Christian

0x2018d28 <swi_handler__Fi>:	mov	r12, sp
0x2018d2c <swi_handler__Fi+4>:	stmdb	sp!, {r11, r12, lr, pc}
0x2018d30 <swi_handler__Fi+8>:	sub	r11, r12, #4	; 0x4
0x2018d34 <swi_handler__Fi+12>:	sub	sp, sp, #12	; 0xc
0x2018d38 <swi_handler__Fi+16>:	str	r0, [r11, -#16]
0x2018d3c <swi_handler__Fi+20>:	mov	r3, #68	; 0x44
0x2018d40 <swi_handler__Fi+24>:	str	r3, [r11, -#20]
0x2018d44 <swi_handler__Fi+28>:	ldr	r3, [r11, -#16]
0x2018d48 <swi_handler__Fi+32>:	cmp	r3, #1	; 0x1
0x2018d4c <swi_handler__Fi+36>:	beq	0x2018d54 <swi_handler__Fi+44>
0x2018d50 <swi_handler__Fi+40>:	b	0x2018d8c <swi_handler__Fi+100>
0x2018d54 <swi_handler__Fi+44>:	mrs	r0, cpsr
0x2018d58 <swi_handler__Fi+48>:	orr	r0, r0, #192	; 0xc0
0x2018d5c <swi_handler__Fi+52>:	msr	cpsr_all, r0
0x2018d60 <swi_handler__Fi+56>:	mrs	r3, cpsr
0x2018d64 <swi_handler__Fi+60>:	str	r3, [r11, -#24]
0x2018d68 <swi_handler__Fi+64>:	ldr	r3, [r11, -#20]
0x2018d6c <swi_handler__Fi+68>:	ldr	r2, [r11, -#24]
0x2018d70 <swi_handler__Fi+72>:	str	r2, [r3]
0x2018d74 <swi_handler__Fi+76>:	mvn	r3, #65280	; 0xff00
0x2018d78 <swi_handler__Fi+80>:	sub	r3, r3, #207	; 0xcf
0x2018d7c <swi_handler__Fi+84>:	str	r3, [r11, -#20]
0x2018d80 <swi_handler__Fi+88>:	ldr	r3, [r11, -#20]
0x2018d84 <swi_handler__Fi+92>:	mov	r2, #22	; 0x16
0x2018d88 <swi_handler__Fi+96>:	str	r2, [r3]
0x2018d8c <swi_handler__Fi+100>:	b	0x2018d90 <swi_handler__Fi+104>
0x2018d90 <swi_handler__Fi+104>:	b	0x2018d98 <swi_handler__Fi+112>
0x2018d94 <swi_handler__Fi+108>:	b	0x2018d98 <swi_handler__Fi+112>
0x2018d98 <swi_handler__Fi+112>:	ldmdb	r11, {r11, sp, pc}


> 
> 
> 
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-- 


Jens-Christian Lache
Technische Universitaet Hamburg-Harburg
www.tu-harburg.de/~sejl1601
Mail:
lache@tu-harburg.de
lache@ngi.de
Tel.:
+0491759610756

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