8. Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where as runs. Floating point representations vary as well, and as often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of as support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.

8.2 AMD 29K Dependent Features
8.1 ARC Dependent Features
8.3 ARM Dependent Features
8.4 D10V Dependent Features
8.5 D30V Dependent Features
8.6 H8/300 Dependent Features		Hitachi H8/300 Dependent Features
8.7 H8/500 Dependent Features		Hitachi H8/500 Dependent Features
8.8 HPPA Dependent Features
8.9 ESA/390 Dependent Features		IBM ESA/390 Dependent Features
8.10 80386 Dependent Features		Intel 80386 Dependent Features
8.11 Intel 80960 Dependent Features
8.12 M680x0 Dependent Features
8.13 MIPS Dependent Features
8.15 Hitachi SH Dependent Features
8.14 picoJava Dependent Features
8.16 SPARC Dependent Features
8.19 v850 Dependent Features		V850 Dependent Features
8.17 Z8000 Dependent Features
8.18 VAX Dependent Features

8.1 ARC Dependent Features

8.1.1 Options
8.1.2 Floating Point
8.1.3 ARC Machine Directives		Sparc Machine Directives

8.1.1 Options

The ARC chip family includes several successive levels (or other variants) of chip, using the same core instruction set, but including a few additional instructions at each level.

By default, as assumes the core instruction set (ARC base). The .cpu pseudo-op is intended to be used to select the variant.

-mbig-endian

-mlittle-endian

Any ARC configuration of as can select big-endian or little-endian output at run time (unlike most other GNU development tools, which must be configured for one or the other). Use `-mbig-endian' to select big-endian output, and `-mlittle-endian' for little-endian.

8.1.2 Floating Point

The ARC cpu family currently does not have hardware floating point support. Software floating point support is provided by GCC and uses IEEE floating-point numbers.

8.1.3 ARC Machine Directives

The ARC version of as supports the following additional machine directives:

.cpu

This must be followed by the desired cpu. The ARC is intended to be customizable, .cpu is used to select the desired variant [though currently there are none].

8.2 AMD 29K Dependent Features

8.2.1 Options
8.2.2 Syntax
8.2.3 Floating Point
8.2.4 AMD 29K Machine Directives
8.2.5 Opcodes

8.2.1 Options

8.2.2 Syntax

8.2.2.1 Macros
8.2.2.2 Special Characters
8.2.2.3 Register Names

8.2.2.1 Macros

The macro syntax used on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Specification. Normal as macros should still work.

8.2.2.2 Special Characters

`;' is the line comment character.

The character `?' is permitted in identifiers (but may not begin an identifier).

8.2.2.3 Register Names

General-purpose registers are represented by predefined symbols of the form `GRnnn' (for global registers) or `LRnnn' (for local registers), where nnn represents a number between 0 and 127, written with no leading zeros. The leading letters may be in either upper or lower case; for example, `gr13' and `LR7' are both valid register names.

You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with `%%' to flag the expression as a register number):

%%expression

---where expression must be an absolute expression evaluating to a number between 0 and 255. The range [0, 127] refers to global registers, and the range [128, 255] to local registers.

In addition, as understands the following protected special-purpose register names for the AMD 29K family:

vab chd pc0 ops chc pc1 cps rbp pc2 cfg tmc mmu cha tmr lru

These unprotected special-purpose register names are also recognized:

ipc alu fpe ipa bp inte ipb fc fps q cr exop

8.2.3 Floating Point

The AMD 29K family uses IEEE floating-point numbers.

8.2.4 AMD 29K Machine Directives

.block size , fill

This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero.

In other versions of the GNU assembler, this directive is called `.space'.

.cputype

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.file

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

Warning: in other versions of the GNU assembler, .file is used for the directive called .app-file in the AMD 29K support.

.line

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.sect

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.use section name

Establishes the section and subsection for the following code; section name may be one of .text, .data, .data1, or .lit. With one of the first three section name options, `.use' is equivalent to the machine directive section name; the remaining case, `.use .lit', is the same as `.data 200'.

8.2.5 Opcodes

as implements all the standard AMD 29K opcodes. No additional pseudo-instructions are needed on this family.

For information on the 29K machine instruction set, see Am29000 User's Manual, Advanced Micro Devices, Inc.

8.3 ARM Dependent Features

8.3.1 Options
8.3.2 Syntax
8.3.3 Floating Point
8.3.4 ARM Machine Directives
8.3.5 Opcodes

8.3.1 Options

-marm[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]

This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.

-marmv[2|2a|3|3m|4|4t|5|5t]

This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture.

-mthumb

This option specifies that only Thumb instructions should be assembled.

-mall

This option specifies that any Arm or Thumb instruction should be assembled.

-mfpa [10|11]

This option specifies the floating point architecture in use on the target processor.

-mfpe-old

Do not allow the assemble of floating point multiple instructions.

-mno-fpu

Do not allow the assembly of any floating point instructions.

-mthumb-interwork

This option specifies that the output generated by the assembler should be marked as supporting interworking.

-mapcs [26|32]

This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.

-mapcs-float

This indicates the the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers.

-mapcs-reentrant

This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.

-EB

This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL

This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

-k

This option enables the generation of PIC (position independent code).

-moabi

This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF specifications, rather than the default conventions which are based on the final release of the ARM-ELF specifications.

8.3.2 Syntax

8.3.2.1 Special Characters
8.3.2.2 Register Names

8.3.2.1 Special Characters

The presence of a `@' on a line indicates the start of a comment that extends to the end of the current line. If a `#' appears as the first character of a line, the whole line is treated as a comment.

On ARM systems running the GNU/Linux operating system, `;' can be used instead of a newline to separate statements.

Either `#' or `$' can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

8.3.2.2 Register Names

*TODO* Explain about ARM register naming, and the predefined names.

8.3.3 Floating Point

The ARM family uses IEEE floating-point numbers.

8.3.4 ARM Machine Directives

.align expression [, expression]

This is the generic .align directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatability with ARM's own assembler.

name .req register name

This creates an alias for register name called name. For example:

foo .req r0

.code [16|32]

This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

.thumb

This performs the same action as .code 16.

.arm

This performs the same action as .code 32.

.force_thumb

This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

.thumb_func

This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed.

.thumb_set

This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined). This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.

.ltorg

This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary).

.pool

This is a synonym for .ltorg.

8.3.5 Opcodes

as implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions.

NOP

nop

This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.

LDR

ldr <register> , = <expression>

If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

ADR

adr <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.

ADRL

adrl <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two a PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

8.4 D10V Dependent Features

8.4.1 D10V Options
8.4.2 Syntax
8.4.3 Floating Point
8.4.4 Opcodes

8.4.1 D10V Options

`-O'

The D10V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`--nowarnswap'

To optimize execution performance, as will sometimes swap the order of instructions. Normally this generates a warning. When this option is used, no warning will be generated when instructions are swapped.

8.4.2 Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

8.4.2.1 Size Modifiers
8.4.2.2 Sub-Instructions
8.4.2.3 Special Characters
8.4.2.4 Register Names
8.4.2.5 Addressing Modes
8.4.2.6 @WORD Modifier

8.4.2.1 Size Modifiers

8.4.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

8.4.2.3 Special Characters

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

abs a1 -> abs r0

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r0 <- abs a1

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

ld2w r2,@r8+ || mac a0,r0,r7

Execute these in parallel.

ld2w r2,@r8+ ||

mac a0,r0,r7

Two-line format. Execute these in parallel.

ld2w r2,@r8+

mac a0,r0,r7

Two-line format. Execute these sequentially. Assembler will put them in the proper containers.

ld2w r2,@r8+ ->

mac a0,r0,r7

Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container.

8.4.2.4 Register Names

Register Pairs

r0-r1

r2-r3

r4-r5

r6-r7

r8-r9

r10-r11

r12-r13

r14-r15

The D10V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

c

Carry flag

8.4.2.5 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

8.4.2.6 @WORD Modifier

ldi     r2, main@word
jmp     r2

8.4.3 Floating Point

8.4.4 Opcodes

8.5 D30V Dependent Features

8.5.1 D30V Options
8.5.2 Syntax
8.5.3 Floating Point
8.5.4 Opcodes

8.5.1 D30V Options

`-O'

The D30V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`-n'

When this option is used, as will issue a warning every time it adds a nop instruction.

`-N'

When this option is used, as will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

8.5.2 Syntax

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

8.5.2.1 Size Modifiers
8.5.2.2 Sub-Instructions
8.5.2.3 Special Characters
8.5.2.4 Guarded Execution
8.5.2.5 Register Names
8.5.2.6 Addressing Modes

8.5.2.1 Size Modifiers

8.5.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

8.5.2.3 Special Characters

To specify the executing order, use the following symbols:

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

abs r2,r3 -> abs r4,r5

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r2,r3 <- abs r4,r5

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

abs r2,r3 || abs r4,r5

Execute these in parallel.

ldw r2,@(r3,r4) ||

mulx r6,r8,r9

Two-line format. Execute these in parallel.

mulx a0,r8,r9

stw r2,@(r3,r4)

Two-line format. Execute these sequentially unless `-O' option is used. If the `-O' option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers. In the above example, the assembler will put the `stw' instruction in left container and the `mulx' instruction in the right container.

stw r2,@(r3,r4) ->

mulx a0,r8,r9

Two-line format. Execute the `stw' instruction followed by the `mulx' instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.

stw r2,@(r3,r4) <-

mulx a0,r8,r9

Same as previous example, except that the `mulx' instruction is executed before the `stw' instruction.

Since `$' has no special meaning, you may use it in symbol names.

8.5.2.4 Guarded Execution

`/tx'

Execute the instruction if flag f0 is true.

`/fx'

Execute the instruction if flag f0 is false.

`/xt'

Execute the instruction if flag f1 is true.

`/xf'

Execute the instruction if flag f1 is false.

`/tt'

Execute the instruction if both flags f0 and f1 are true.

`/tf'

Execute the instruction if flag f0 is true and flag f1 is false.

8.5.2.5 Register Names

The D30V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

f2

Flag 2

f3

Flag 3

f4

Flag 4

f5

Flag 5

f6

Flag 6

f7

Flag 7

s

Same as flag 4 (saturation flag)

v

Same as flag 5 (overflow flag)

va

Same as flag 6 (sticky overflow flag)

c

Same as flag 7 (carry/borrow flag)

b

Same as flag 7 (carry/borrow flag)

8.5.2.6 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

8.5.3 Floating Point

8.5.4 Opcodes

8.6 H8/300 Dependent Features

8.6.1 Options
8.6.2 Syntax
8.6.3 Floating Point
8.6.4 H8/300 Machine Directives
8.6.5 Opcodes

8.6.1 Options

as has no additional command-line options for the Hitachi H8/300 family.

8.6.2 Syntax

8.6.2.1 Special Characters
8.6.2.2 Register Names
8.6.2.3 Addressing Modes

8.6.2.1 Special Characters

`;' is the line comment character.

`$' can be used instead of a newline to separate statements. Therefore you may not use `$' in symbol names on the H8/300.

8.6.2.2 Register Names

You can use predefined symbols of the form `rnh' and `rnl' to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid register names.

You can also use the eight predefined symbols `rn' to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols `ern' (`er0' ... `er7') to refer to the 32-bit general purpose registers.

The two control registers are called pc (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and ccr (condition code register; an 8-bit register). r7 is used as the stack pointer, and can also be called sp.

8.6.2.3 Addressing Modes

as understands the following addressing modes for the H8/300:

rn

Register direct

@rn

Register indirect

@(d, rn)

@(d:16, rn)

@(d:24, rn)

Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit displacements are only meaningful on the H8/300H.)

@rn+

Register indirect with post-increment

@-rn

Register indirect with pre-decrement

@aa

@aa:8

@aa:16

@aa:24

Absolute address aa. (The address size `:24' only makes sense on the H8/300H.)

#xx

#xx:8

#xx:16

#xx:32

Immediate data xx. You may specify the `:8', `:16', or `:32' for clarity, if you wish; but as neither requires this nor uses it--the data size required is taken from context.

@@aa

@@aa:8

Memory indirect. You may specify the `:8' for clarity, if you wish; but as neither requires this nor uses it.

8.6.3 Floating Point

The H8/300 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

8.6.4 H8/300 Machine Directives

as has only one machine-dependent directive for the H8/300:

.h8300h

Recognize and emit additional instructions for the H8/300H variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) `.word' directives generate 16-bit numbers.

8.6.5 Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual (Hitachi ADE--602--025). For information specific to the H8/300H, see H8/300H Series Programming Manual (Hitachi).

as implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes the H8/300 opcodes, and their arguments. Entries marked `*' are opcodes used only on the H8/300H.

Legend: Rs source register Rd destination register abs absolute address imm immediate data disp:N N-bit displacement from a register pcrel:N N-bit displacement relative to program counter add.b #imm,rd * andc #imm,ccr add.b rs,rd band #imm,rd add.w rs,rd band #imm,@rd * add.w #imm,rd band #imm,@abs:8 * add.l rs,rd bra pcrel:8 * add.l #imm,rd * bra pcrel:16 adds #imm,rd bt pcrel:8 addx #imm,rd * bt pcrel:16 addx rs,rd brn pcrel:8 and.b #imm,rd * brn pcrel:16 and.b rs,rd bf pcrel:8 * and.w rs,rd * bf pcrel:16 * and.w #imm,rd bhi pcrel:8 * and.l #imm,rd * bhi pcrel:16 * and.l rs,rd bls pcrel:8 * bls pcrel:16 bld #imm,rd bcc pcrel:8 bld #imm,@rd * bcc pcrel:16 bld #imm,@abs:8 bhs pcrel:8 bnot #imm,rd * bhs pcrel:16 bnot #imm,@rd bcs pcrel:8 bnot #imm,@abs:8 * bcs pcrel:16 bnot rs,rd blo pcrel:8 bnot rs,@rd * blo pcrel:16 bnot rs,@abs:8 bne pcrel:8 bor #imm,rd * bne pcrel:16 bor #imm,@rd beq pcrel:8 bor #imm,@abs:8 * beq pcrel:16 bset #imm,rd bvc pcrel:8 bset #imm,@rd * bvc pcrel:16 bset #imm,@abs:8 bvs pcrel:8 bset rs,rd * bvs pcrel:16 bset rs,@rd bpl pcrel:8 bset rs,@abs:8 * bpl pcrel:16 bsr pcrel:8 bmi pcrel:8 bsr pcrel:16 * bmi pcrel:16 bst #imm,rd bge pcrel:8 bst #imm,@rd * bge pcrel:16 bst #imm,@abs:8 blt pcrel:8 btst #imm,rd * blt pcrel:16 btst #imm,@rd bgt pcrel:8 btst #imm,@abs:8 * bgt pcrel:16 btst rs,rd ble pcrel:8 btst rs,@rd * ble pcrel:16 btst rs,@abs:8 bclr #imm,rd bxor #imm,rd bclr #imm,@rd bxor #imm,@rd bclr #imm,@abs:8 bxor #imm,@abs:8 bclr rs,rd cmp.b #imm,rd bclr rs,@rd cmp.b rs,rd bclr rs,@abs:8 cmp.w rs,rd biand #imm,rd cmp.w rs,rd biand #imm,@rd * cmp.w #imm,rd biand #imm,@abs:8 * cmp.l #imm,rd bild #imm,rd * cmp.l rs,rd bild #imm,@rd daa rs bild #imm,@abs:8 das rs bior #imm,rd dec.b rs bior #imm,@rd * dec.w #imm,rd bior #imm,@abs:8 * dec.l #imm,rd bist #imm,rd divxu.b rs,rd bist #imm,@rd * divxu.w rs,rd bist #imm,@abs:8 * divxs.b rs,rd bixor #imm,rd * divxs.w rs,rd bixor #imm,@rd eepmov bixor #imm,@abs:8 * eepmovw * exts.w rd mov.w rs,@abs:16 * exts.l rd * mov.l #imm,rd * extu.w rd * mov.l rs,rd * extu.l rd * mov.l @rs,rd inc rs * mov.l @(disp:16,rs),rd * inc.w #imm,rd * mov.l @(disp:24,rs),rd * inc.l #imm,rd * mov.l @rs+,rd jmp @rs * mov.l @abs:16,rd jmp abs * mov.l @abs:24,rd jmp @@abs:8 * mov.l rs,@rd jsr @rs * mov.l rs,@(disp:16,rd) jsr abs * mov.l rs,@(disp:24,rd) jsr @@abs:8 * mov.l rs,@-rd ldc #imm,ccr * mov.l rs,@abs:16 ldc rs,ccr * mov.l rs,@abs:24 * ldc @abs:16,ccr movfpe @abs:16,rd * ldc @abs:24,ccr movtpe rs,@abs:16 * ldc @(disp:16,rs),ccr mulxu.b rs,rd * ldc @(disp:24,rs),ccr * mulxu.w rs,rd * ldc @rs+,ccr * mulxs.b rs,rd * ldc @rs,ccr * mulxs.w rs,rd * mov.b @(disp:24,rs),rd neg.b rs * mov.b rs,@(disp:24,rd) * neg.w rs mov.b @abs:16,rd * neg.l rs mov.b rs,rd nop mov.b @abs:8,rd not.b rs mov.b rs,@abs:8 * not.w rs mov.b rs,rd * not.l rs mov.b #imm,rd or.b #imm,rd mov.b @rs,rd or.b rs,rd mov.b @(disp:16,rs),rd * or.w #imm,rd mov.b @rs+,rd * or.w rs,rd mov.b @abs:8,rd * or.l #imm,rd mov.b rs,@rd * or.l rs,rd mov.b rs,@(disp:16,rd) orc #imm,ccr mov.b rs,@-rd pop.w rs mov.b rs,@abs:8 * pop.l rs mov.w rs,@rd push.w rs * mov.w @(disp:24,rs),rd * push.l rs * mov.w rs,@(disp:24,rd) rotl.b rs * mov.w @abs:24,rd * rotl.w rs * mov.w rs,@abs:24 * rotl.l rs mov.w rs,rd rotr.b rs mov.w #imm,rd * rotr.w rs mov.w @rs,rd * rotr.l rs mov.w @(disp:16,rs),rd rotxl.b rs mov.w @rs+,rd * rotxl.w rs mov.w @abs:16,rd * rotxl.l rs mov.w rs,@(disp:16,rd) rotxr.b rs mov.w rs,@-rd * rotxr.w rs * rotxr.l rs * stc ccr,@(disp:24,rd) bpt * stc ccr,@-rd rte * stc ccr,@abs:16 rts * stc ccr,@abs:24 shal.b rs sub.b rs,rd * shal.w rs sub.w rs,rd * shal.l rs * sub.w #imm,rd shar.b rs * sub.l rs,rd * shar.w rs * sub.l #imm,rd * shar.l rs subs #imm,rd shll.b rs subx #imm,rd * shll.w rs subx rs,rd * shll.l rs * trapa #imm shlr.b rs xor #imm,rd * shlr.w rs xor rs,rd * shlr.l rs * xor.w #imm,rd sleep * xor.w rs,rd stc ccr,rd * xor.l #imm,rd * stc ccr,@rs * xor.l rs,rd * stc ccr,@(disp:16,rd) xorc #imm,ccr

Four H8/300 instructions (add, cmp, mov, sub) are defined with variants using the suffixes `.b', `.w', and `.l' to specify the size of a memory operand. as supports these suffixes, but does not require them; since one of the operands is always a register, as can deduce the correct size.

For example, since r0 refers to a 16-bit register,

mov r0,@foo is equivalent to mov.w r0,@foo

If you use the size suffixes, as issues a warning when the suffix and the register size do not match.

8.7 H8/500 Dependent Features

8.7.1 Options
8.7.2 Syntax
8.7.3 Floating Point
8.7.4 H8/500 Machine Directives
8.7.5 Opcodes

8.7.1 Options

as has no additional command-line options for the Hitachi H8/500 family.

8.7.2 Syntax

8.7.2.1 Special Characters
8.7.2.2 Register Names
8.7.2.3 Addressing Modes

8.7.2.1 Special Characters

`!' is the line comment character.

`;' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

8.7.2.2 Register Names

You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', `r6', and `r7' to refer to the H8/500 registers.

The H8/500 also has these control registers:

cp

code pointer

dp

data pointer

bp

base pointer

tp

stack top pointer

ep

extra pointer

sr

status register

ccr

condition code register

All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (cp for the program counter; dp for r0--r3; ep for r4 and r5; and tp for r6 and r7.

8.7.2.3 Addressing Modes

as understands the following addressing modes for the H8/500:

Rn

Register direct

@Rn

Register indirect

@(d:8, Rn)

Register indirect with 8 bit signed displacement

@(d:16, Rn)

Register indirect with 16 bit signed displacement

@-Rn

Register indirect with pre-decrement

@Rn+

Register indirect with post-increment

@aa:8

8 bit absolute address

@aa:16

16 bit absolute address

#xx:8

8 bit immediate

#xx:16

16 bit immediate

8.7.3 Floating Point

The H8/500 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

8.7.4 H8/500 Machine Directives

as has no machine-dependent directives for the H8/500. However, on this platform the `.int' and `.word' directives generate 16-bit numbers.

8.7.5 Opcodes

For detailed information on the H8/500 machine instruction set, see H8/500 Series Programming Manual (Hitachi M21T001).

as implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes H8/500 opcodes and their operands:

Legend: abs8 8-bit absolute address abs16 16-bit absolute address abs24 24-bit absolute address crb ccr, br, ep, dp, tp, dp disp8 8-bit displacement ea rn, @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16, #xx:8, #xx:16 ea_mem @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16 ea_noimm rn, @rn, @(d:8, rn), @(d:16, rn), @-rn, @rn+, @aa:8, @aa:16 fp r6 imm4 4-bit immediate data imm8 8-bit immediate data imm16 16-bit immediate data pcrel8 8-bit offset from program counter pcrel16 16-bit offset from program counter qim -2, -1, 1, 2 rd any register rs a register distinct from rd rlist comma-separated list of registers in parentheses; register ranges rd-rs are allowed sp stack pointer (r7) sr status register sz size; `.b' or `.w'. If omitted, default `.w' ldc[.b] ea,crb bcc[.w] pcrel16 ldc[.w] ea,sr bcc[.b] pcrel8 add[:q] sz qim,ea_noimm bhs[.w] pcrel16 add[:g] sz ea,rd bhs[.b] pcrel8 adds sz ea,rd bcs[.w] pcrel16 addx sz ea,rd bcs[.b] pcrel8 and sz ea,rd blo[.w] pcrel16 andc[.b] imm8,crb blo[.b] pcrel8 andc[.w] imm16,sr bne[.w] pcrel16 bpt bne[.b] pcrel8 bra[.w] pcrel16 beq[.w] pcrel16 bra[.b] pcrel8 beq[.b] pcrel8 bt[.w] pcrel16 bvc[.w] pcrel16 bt[.b] pcrel8 bvc[.b] pcrel8 brn[.w] pcrel16 bvs[.w] pcrel16 brn[.b] pcrel8 bvs[.b] pcrel8 bf[.w] pcrel16 bpl[.w] pcrel16 bf[.b] pcrel8 bpl[.b] pcrel8 bhi[.w] pcrel16 bmi[.w] pcrel16 bhi[.b] pcrel8 bmi[.b] pcrel8 bls[.w] pcrel16 bge[.w] pcrel16 bls[.b] pcrel8 bge[.b] pcrel8 blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem bgt[.w] pcrel16 movfpe[.b] ea,rd bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm ble[.w] pcrel16 mulxu sz ea,rd ble[.b] pcrel8 neg sz ea bclr sz imm4,ea_noimm nop bclr sz rs,ea_noimm not sz ea bnot sz imm4,ea_noimm or sz ea,rd bnot sz rs,ea_noimm orc[.b] imm8,crb bset sz imm4,ea_noimm orc[.w] imm16,sr bset sz rs,ea_noimm pjmp abs24 bsr[.b] pcrel8 pjm